From: "Heiko Stübner" <heiko@sntech.de>
To: Palmer Dabbelt <palmer@rivosinc.com>, Evan Green <evan@rivosinc.com>
Cc: slewis@rivosinc.com, Conor Dooley <conor@kernel.org>,
vineetg@rivosinc.com, Evan Green <evan@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Bresticker <abrestic@rivosinc.com>,
Celeste Liu <coelacanthus@outlook.com>,
Guo Ren <guoren@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA
Date: Tue, 21 Mar 2023 21:25:56 +0100 [thread overview]
Message-ID: <22291092.EfDdHjke4D@diego> (raw)
In-Reply-To: <20230314183220.513101-4-evan@rivosinc.com>
Am Dienstag, 14. März 2023, 19:32:17 CET schrieb Evan Green:
> We have an implicit set of base behaviors that userspace depends on,
> which are mostly defined in various ISA specifications.
>
> Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
This needs one fix, described blow, with that applied:
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> + case RISCV_HWPROBE_KEY_IMA_EXT_0:
> + pair->value = 0;
> + if (has_fpu())
> + pair->value |= RISCV_HWPROBE_IMA_FD;
> +
> + if (elf_hwcap & RISCV_ISA_EXT_c)
This wants to be
if (elf_hwcap & riscv_isa_extension_mask(c))
i.e. elf_hwcap is a bitmap, RISCV_ISA_EXT_c is the number "2" and
riscv_isa_extension_mask() will get you the shifted bit.
> + pair->value |= RISCV_HWPROBE_IMA_C;
> +
> + break;
>
> /*
> * For forward compatibility, unknown keys don't fail the whole
>
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Palmer Dabbelt <palmer@rivosinc.com>, Evan Green <evan@rivosinc.com>
Cc: slewis@rivosinc.com, Conor Dooley <conor@kernel.org>,
vineetg@rivosinc.com, Evan Green <evan@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Bresticker <abrestic@rivosinc.com>,
Celeste Liu <coelacanthus@outlook.com>,
Guo Ren <guoren@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA
Date: Tue, 21 Mar 2023 21:25:56 +0100 [thread overview]
Message-ID: <22291092.EfDdHjke4D@diego> (raw)
In-Reply-To: <20230314183220.513101-4-evan@rivosinc.com>
Am Dienstag, 14. März 2023, 19:32:17 CET schrieb Evan Green:
> We have an implicit set of base behaviors that userspace depends on,
> which are mostly defined in various ISA specifications.
>
> Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
This needs one fix, described blow, with that applied:
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> + case RISCV_HWPROBE_KEY_IMA_EXT_0:
> + pair->value = 0;
> + if (has_fpu())
> + pair->value |= RISCV_HWPROBE_IMA_FD;
> +
> + if (elf_hwcap & RISCV_ISA_EXT_c)
This wants to be
if (elf_hwcap & riscv_isa_extension_mask(c))
i.e. elf_hwcap is a bitmap, RISCV_ISA_EXT_c is the number "2" and
riscv_isa_extension_mask() will get you the shifted bit.
> + pair->value |= RISCV_HWPROBE_IMA_C;
> +
> + break;
>
> /*
> * For forward compatibility, unknown keys don't fail the whole
>
Heiko
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next prev parent reply other threads:[~2023-03-21 20:26 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 18:32 [PATCH v4 0/6] RISC-V Hardware Probing User Interface Evan Green
2023-03-14 18:32 ` [PATCH v4 1/6] RISC-V: Move struct riscv_cpuinfo to new header Evan Green
2023-03-14 18:32 ` Evan Green
2023-03-21 20:22 ` Heiko Stübner
2023-03-21 20:22 ` Heiko Stübner
2023-03-14 18:32 ` [PATCH v4 2/6] RISC-V: Add a syscall for HW probing Evan Green
2023-03-14 18:32 ` Evan Green
2023-03-21 20:23 ` Heiko Stübner
2023-03-21 20:23 ` Heiko Stübner
2023-03-14 18:32 ` [PATCH v4 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green
2023-03-14 18:32 ` Evan Green
2023-03-21 16:41 ` Heiko Stübner
2023-03-21 16:41 ` Heiko Stübner
2023-03-22 16:17 ` Evan Green
2023-03-22 16:17 ` Evan Green
2023-03-21 20:25 ` Heiko Stübner [this message]
2023-03-21 20:25 ` Heiko Stübner
2023-03-22 15:35 ` Conor Dooley
2023-03-22 15:35 ` Conor Dooley
2023-03-22 16:04 ` Evan Green
2023-03-22 16:04 ` Evan Green
2023-03-14 18:32 ` [PATCH v4 4/6] RISC-V: hwprobe: Support probing of misaligned access performance Evan Green
2023-03-14 18:32 ` Evan Green
2023-03-17 10:08 ` Heiko Stübner
2023-03-17 10:08 ` Heiko Stübner
2023-03-21 15:35 ` Evan Green
2023-03-21 15:35 ` Evan Green
2023-03-18 12:02 ` Conor Dooley
2023-03-18 12:02 ` Conor Dooley
2023-03-21 20:27 ` Heiko Stübner
2023-03-21 20:27 ` Heiko Stübner
2023-03-14 18:32 ` [PATCH v4 5/6] selftests: Test the new RISC-V hwprobe interface Evan Green
2023-03-14 18:32 ` Evan Green
2023-03-14 18:32 ` [PATCH v4 6/6] RISC-V: Add hwprobe vDSO function and data Evan Green
2023-03-14 18:32 ` Evan Green
2023-03-17 11:08 ` kernel test robot
2023-03-17 11:08 ` kernel test robot
2023-03-17 12:10 ` kernel test robot
2023-03-17 12:10 ` kernel test robot
2023-03-21 20:32 ` [PATCH v4 0/6] RISC-V Hardware Probing User Interface Heiko Stübner
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