From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: Andre Przywara <andre.przywara@arm.com>,
Maksim Kiselev <bigunclemax@gmail.com>
Cc: Icenowy Zheng <icenowy@aosc.io>,
Maksim Kiselev <bigunclemax@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Samuel Holland <samuel@sholland.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
Maxime Ripard <mripard@kernel.org>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v5 3/5] spi: sun6i: add quirk for in-controller clock divider
Date: Thu, 11 May 2023 18:38:58 +0200 [thread overview]
Message-ID: <23071886.6Emhk5qWAg@jernej-laptop> (raw)
In-Reply-To: <20230510081121.3463710-4-bigunclemax@gmail.com>
Dne sreda, 10. maj 2023 ob 10:11:10 CEST je Maksim Kiselev napisal(a):
> Previously SPI controllers in Allwinner SoCs has a clock divider inside.
> However now the clock divider is removed and to set the transfer clock
> rate it's only needed to set the SPI module clock to the target value
> and configure a proper work mode.
>
> According to the datasheet there are three work modes:
> | SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock |
> |
> |-------------------------|------------|------------|-----------|
> |
> | normal sample | 1 | 0 | <= 24 MHz |
> | delay half cycle sample | 0 | 0 | <= 40 MHz |
> | delay one cycle sample | 0 | 1 | >= 80 MHz |
>
> Add a quirk for this kind of SPI controllers.
>
> Co-developed-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
WARNING: multiple messages have this Message-ID (diff)
From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: Andre Przywara <andre.przywara@arm.com>,
Maksim Kiselev <bigunclemax@gmail.com>
Cc: Icenowy Zheng <icenowy@aosc.io>,
Maksim Kiselev <bigunclemax@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Samuel Holland <samuel@sholland.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
Maxime Ripard <mripard@kernel.org>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v5 3/5] spi: sun6i: add quirk for in-controller clock divider
Date: Thu, 11 May 2023 18:38:58 +0200 [thread overview]
Message-ID: <23071886.6Emhk5qWAg@jernej-laptop> (raw)
In-Reply-To: <20230510081121.3463710-4-bigunclemax@gmail.com>
Dne sreda, 10. maj 2023 ob 10:11:10 CEST je Maksim Kiselev napisal(a):
> Previously SPI controllers in Allwinner SoCs has a clock divider inside.
> However now the clock divider is removed and to set the transfer clock
> rate it's only needed to set the SPI module clock to the target value
> and configure a proper work mode.
>
> According to the datasheet there are three work modes:
> | SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock |
> |
> |-------------------------|------------|------------|-----------|
> |
> | normal sample | 1 | 0 | <= 24 MHz |
> | delay half cycle sample | 0 | 0 | <= 40 MHz |
> | delay one cycle sample | 0 | 1 | >= 80 MHz |
>
> Add a quirk for this kind of SPI controllers.
>
> Co-developed-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
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next prev parent reply other threads:[~2023-05-11 16:39 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-10 8:11 [PATCH v5 0/5] Allwinner R329/D1/R528/T113s SPI support Maksim Kiselev
2023-05-10 8:11 ` Maksim Kiselev
2023-05-10 8:11 ` [PATCH v5 1/5] dt-bindings: spi: sun6i: add DT bindings for Allwinner R329/D1/R528/T113s SPI Maksim Kiselev
2023-05-10 8:11 ` Maksim Kiselev
2023-05-10 10:33 ` Andre Przywara
2023-05-10 10:33 ` Andre Przywara
2023-05-11 16:39 ` Jernej Škrabec
2023-05-11 16:39 ` Jernej Škrabec
2023-05-10 8:11 ` [PATCH v5 2/5] spi: sun6i: change OF match data to a struct Maksim Kiselev
2023-05-10 8:11 ` Maksim Kiselev
2023-05-11 16:39 ` Jernej Škrabec
2023-05-11 16:39 ` Jernej Škrabec
2023-05-10 8:11 ` [PATCH v5 3/5] spi: sun6i: add quirk for in-controller clock divider Maksim Kiselev
2023-05-10 8:11 ` Maksim Kiselev
2023-05-11 13:42 ` Andre Przywara
2023-05-11 13:42 ` Andre Przywara
2023-05-11 16:38 ` Jernej Škrabec [this message]
2023-05-11 16:38 ` Jernej Škrabec
2023-05-10 8:11 ` [PATCH v5 4/5] spi: sun6i: add support for R329/D1/R528/T113s SPI controllers Maksim Kiselev
2023-05-10 8:11 ` Maksim Kiselev
2023-05-10 21:05 ` Jernej Škrabec
2023-05-10 21:05 ` Jernej Škrabec
2023-05-10 8:11 ` [PATCH v5 5/5] riscv: dts: allwinner: d1: Add SPI controllers node Maksim Kiselev
2023-05-10 8:11 ` Maksim Kiselev
2023-05-10 20:59 ` Jernej Škrabec
2023-05-10 20:59 ` Jernej Škrabec
2023-05-18 21:12 ` Jernej Škrabec
2023-05-18 21:12 ` Jernej Škrabec
2023-05-18 21:12 ` Jernej Škrabec
2023-05-12 5:24 ` (subset) [PATCH v5 0/5] Allwinner R329/D1/R528/T113s SPI support Mark Brown
2023-05-12 5:24 ` Mark Brown
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