From: Jose Abreu <Jose.Abreu@synopsys.com> To: netdev@vger.kernel.org Cc: Joao Pinto <Joao.Pinto@synopsys.com>, Jose Abreu <Jose.Abreu@synopsys.com>, Giuseppe Cavallaro <peppe.cavallaro@st.com>, Alexandre Torgue <alexandre.torgue@st.com>, Jose Abreu <Jose.Abreu@synopsys.com>, "David S. Miller" <davem@davemloft.net>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/6] net: stmmac: xgmac: Add C45 PHY support in the MDIO callbacks Date: Mon, 11 Nov 2019 15:42:36 +0100 [thread overview] Message-ID: <37a284c640a3e071811fa50838cfe3a319f50fb0.1573482991.git.Jose.Abreu@synopsys.com> (raw) In-Reply-To: <cover.1573482991.git.Jose.Abreu@synopsys.com> In-Reply-To: <cover.1573482991.git.Jose.Abreu@synopsys.com> Add the support for C45 PHYs in the MDIO callbacks for XGMAC. This was tested using Synopsys DesignWare XPCS. v2: - Pull out the readl_poll_timeout() calls into common code (Andrew) Signed-off-by: Jose Abreu <Jose.Abreu@synopsys.com> --- Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Jose Abreu <joabreu@synopsys.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: netdev@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 58 +++++++++++++++++++---- 1 file changed, 48 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index 40c42637ad75..cfe5d8b73142 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -41,20 +41,32 @@ #define MII_XGMAC_BUSY BIT(22) #define MII_XGMAC_MAX_C22ADDR 3 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0) +#define MII_XGMAC_PA_SHIFT 16 +#define MII_XGMAC_DA_SHIFT 21 + +static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr, + int phyreg, u32 *hw_addr) +{ + u32 tmp; + + /* Set port as Clause 45 */ + tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); + tmp &= ~BIT(phyaddr); + writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); + + *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff); + *hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT; + return 0; +} static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, int phyreg, u32 *hw_addr) { - unsigned int mii_data = priv->hw->mii.data; u32 tmp; /* HW does not support C22 addr >= 4 */ if (phyaddr > MII_XGMAC_MAX_C22ADDR) return -ENODEV; - /* Wait until any existing MII operation is complete */ - if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, - !(tmp & MII_XGMAC_BUSY), 100, 10000)) - return -EBUSY; /* Set port as Clause 22 */ tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); @@ -62,7 +74,7 @@ static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, tmp |= BIT(phyaddr); writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); - *hw_addr = (phyaddr << 16) | (phyreg & 0x1f); + *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f); return 0; } @@ -75,17 +87,28 @@ static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) u32 tmp, addr, value = MII_XGMAC_BUSY; int ret; + /* Wait until any existing MII operation is complete */ + if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, + !(tmp & MII_XGMAC_BUSY), 100, 10000)) + return -EBUSY; + if (phyreg & MII_ADDR_C45) { - return -EOPNOTSUPP; + phyreg &= ~MII_ADDR_C45; + + ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr); + if (ret) + return ret; } else { ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); if (ret) return ret; + + value |= MII_XGMAC_SADDR; } value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) & priv->hw->mii.clk_csr_mask; - value |= MII_XGMAC_SADDR | MII_XGMAC_READ; + value |= MII_XGMAC_READ; /* Wait until any existing MII operation is complete */ if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, @@ -115,17 +138,28 @@ static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr, u32 addr, tmp, value = MII_XGMAC_BUSY; int ret; + /* Wait until any existing MII operation is complete */ + if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, + !(tmp & MII_XGMAC_BUSY), 100, 10000)) + return -EBUSY; + if (phyreg & MII_ADDR_C45) { - return -EOPNOTSUPP; + phyreg &= ~MII_ADDR_C45; + + ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr); + if (ret) + return ret; } else { ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); if (ret) return ret; + + value |= MII_XGMAC_SADDR; } value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) & priv->hw->mii.clk_csr_mask; - value |= phydata | MII_XGMAC_SADDR; + value |= phydata; value |= MII_XGMAC_WRITE; /* Wait until any existing MII operation is complete */ @@ -363,6 +397,10 @@ int stmmac_mdio_register(struct net_device *ndev) goto bus_register_fail; } + /* Looks like we need a dummy read for XGMAC only and C45 PHYs */ + if (priv->plat->has_xgmac) + stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45); + if (priv->plat->phy_node || mdio_node) goto bus_register_done; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Jose Abreu <Jose.Abreu@synopsys.com> To: netdev@vger.kernel.org Cc: Jose Abreu <Jose.Abreu@synopsys.com>, Joao Pinto <Joao.Pinto@synopsys.com>, Alexandre Torgue <alexandre.torgue@st.com>, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Giuseppe Cavallaro <peppe.cavallaro@st.com>, "David S. Miller" <davem@davemloft.net>, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next 3/6] net: stmmac: xgmac: Add C45 PHY support in the MDIO callbacks Date: Mon, 11 Nov 2019 15:42:36 +0100 [thread overview] Message-ID: <37a284c640a3e071811fa50838cfe3a319f50fb0.1573482991.git.Jose.Abreu@synopsys.com> (raw) In-Reply-To: <cover.1573482991.git.Jose.Abreu@synopsys.com> In-Reply-To: <cover.1573482991.git.Jose.Abreu@synopsys.com> Add the support for C45 PHYs in the MDIO callbacks for XGMAC. This was tested using Synopsys DesignWare XPCS. v2: - Pull out the readl_poll_timeout() calls into common code (Andrew) Signed-off-by: Jose Abreu <Jose.Abreu@synopsys.com> --- Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Jose Abreu <joabreu@synopsys.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: netdev@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 58 +++++++++++++++++++---- 1 file changed, 48 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index 40c42637ad75..cfe5d8b73142 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -41,20 +41,32 @@ #define MII_XGMAC_BUSY BIT(22) #define MII_XGMAC_MAX_C22ADDR 3 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0) +#define MII_XGMAC_PA_SHIFT 16 +#define MII_XGMAC_DA_SHIFT 21 + +static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr, + int phyreg, u32 *hw_addr) +{ + u32 tmp; + + /* Set port as Clause 45 */ + tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); + tmp &= ~BIT(phyaddr); + writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); + + *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff); + *hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT; + return 0; +} static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, int phyreg, u32 *hw_addr) { - unsigned int mii_data = priv->hw->mii.data; u32 tmp; /* HW does not support C22 addr >= 4 */ if (phyaddr > MII_XGMAC_MAX_C22ADDR) return -ENODEV; - /* Wait until any existing MII operation is complete */ - if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, - !(tmp & MII_XGMAC_BUSY), 100, 10000)) - return -EBUSY; /* Set port as Clause 22 */ tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); @@ -62,7 +74,7 @@ static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, tmp |= BIT(phyaddr); writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); - *hw_addr = (phyaddr << 16) | (phyreg & 0x1f); + *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f); return 0; } @@ -75,17 +87,28 @@ static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) u32 tmp, addr, value = MII_XGMAC_BUSY; int ret; + /* Wait until any existing MII operation is complete */ + if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, + !(tmp & MII_XGMAC_BUSY), 100, 10000)) + return -EBUSY; + if (phyreg & MII_ADDR_C45) { - return -EOPNOTSUPP; + phyreg &= ~MII_ADDR_C45; + + ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr); + if (ret) + return ret; } else { ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); if (ret) return ret; + + value |= MII_XGMAC_SADDR; } value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) & priv->hw->mii.clk_csr_mask; - value |= MII_XGMAC_SADDR | MII_XGMAC_READ; + value |= MII_XGMAC_READ; /* Wait until any existing MII operation is complete */ if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, @@ -115,17 +138,28 @@ static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr, u32 addr, tmp, value = MII_XGMAC_BUSY; int ret; + /* Wait until any existing MII operation is complete */ + if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, + !(tmp & MII_XGMAC_BUSY), 100, 10000)) + return -EBUSY; + if (phyreg & MII_ADDR_C45) { - return -EOPNOTSUPP; + phyreg &= ~MII_ADDR_C45; + + ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr); + if (ret) + return ret; } else { ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); if (ret) return ret; + + value |= MII_XGMAC_SADDR; } value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) & priv->hw->mii.clk_csr_mask; - value |= phydata | MII_XGMAC_SADDR; + value |= phydata; value |= MII_XGMAC_WRITE; /* Wait until any existing MII operation is complete */ @@ -363,6 +397,10 @@ int stmmac_mdio_register(struct net_device *ndev) goto bus_register_fail; } + /* Looks like we need a dummy read for XGMAC only and C45 PHYs */ + if (priv->plat->has_xgmac) + stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45); + if (priv->plat->phy_node || mdio_node) goto bus_register_done; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-11 14:43 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-11 14:42 [PATCH net-next 0/6] net: stmmac: Improvements for -next Jose Abreu 2019-11-11 14:42 ` Jose Abreu 2019-11-11 14:42 ` [PATCH net-next 1/6] net: stmmac: Fix sparse warning Jose Abreu 2019-11-11 14:42 ` Jose Abreu 2019-11-11 14:42 ` [PATCH net-next 2/6] net: stmmac: gmac4+: Add Split Header support Jose Abreu 2019-11-11 14:42 ` Jose Abreu 2019-11-11 14:42 ` Jose Abreu [this message] 2019-11-11 14:42 ` [PATCH net-next 3/6] net: stmmac: xgmac: Add C45 PHY support in the MDIO callbacks Jose Abreu 2019-11-11 14:42 ` [PATCH net-next 4/6] net: stmmac: tc: Remove the speed dependency Jose Abreu 2019-11-11 14:42 ` Jose Abreu 2019-11-11 14:42 ` [PATCH net-next 5/6] net: stmmac: Rework stmmac_rx() Jose Abreu 2019-11-11 14:42 ` Jose Abreu 2019-11-11 14:42 ` [PATCH net-next 6/6] net: stmmac: Implement UDP Segmentation Offload Jose Abreu 2019-11-11 14:42 ` Jose Abreu 2019-11-12 7:13 ` [PATCH net-next 0/6] net: stmmac: Improvements for -next David Miller 2019-11-12 7:13 ` David Miller
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