All of lore.kernel.org
 help / color / mirror / Atom feed
From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	joao.pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com,
	adouglas@cadence.com, jesper.nilsson@axis.com,
	shawn.lin@rock-chips.com
Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Subject: [PATCH v11 01/12] PCI: dwc: Fix EP link notification implementation
Date: Mon, 16 Jul 2018 16:52:13 +0200	[thread overview]
Message-ID: <3cefa89ce2e496e7627bd3c7ade93348230adc14.1531751641.git.gustavo.pimentel@synopsys.com> (raw)
In-Reply-To: <cover.1531751641.git.gustavo.pimentel@synopsys.com>
In-Reply-To: <cover.1531751641.git.gustavo.pimentel@synopsys.com>

Move specific features settings from EP shared code
(pcie-designware-ep.c) to the driver (pcie-designware-plat.c).

Previous implementation disables the EP link notification
by default for all SoCs that uses EP DesignWare IP, which affects
directly the dra7xx and artpec6 SoCs.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Change v8->v9:
 - Created patch file.
Change v9->v10:
 - Nothing changed, just to follow the patch set version.
Change v10->v11:
 - Missed Kishon acknowledge.

 drivers/pci/controller/dwc/pcie-designware-ep.c   | 14 ++++++--------
 drivers/pci/controller/dwc/pcie-designware-plat.c |  3 +++
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 8650416..04092a7 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -386,15 +386,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		return -ENOMEM;
 	ep->outbound_addr = addr;
 
-	if (ep->ops->ep_init)
-		ep->ops->ep_init(ep);
-
 	epc = devm_pci_epc_create(dev, &epc_ops);
 	if (IS_ERR(epc)) {
 		dev_err(dev, "Failed to create epc device\n");
 		return PTR_ERR(epc);
 	}
 
+	ep->epc = epc;
+	epc_set_drvdata(epc, ep);
+
+	if (ep->ops->ep_init)
+		ep->ops->ep_init(ep);
+
 	ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
 	if (ret < 0)
 		epc->max_functions = 1;
@@ -413,11 +416,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		return -ENOMEM;
 	}
 
-	epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER;
-	EPC_FEATURE_SET_BAR(epc->features, BAR_0);
-
-	ep->epc = epc;
-	epc_set_drvdata(epc, ep);
 	dw_pcie_setup(pci);
 
 	return 0;
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 5937fed..0ce3440 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -70,10 +70,13 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct pci_epc *epc = ep->epc;
 	enum pci_barno bar;
 
 	for (bar = BAR_0; bar <= BAR_5; bar++)
 		dw_pcie_ep_reset_bar(pci, bar);
+
+	epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
 }
 
 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	joao.pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com,
	adouglas@cadence.com, jesper.nilsson@axis.com,
	shawn.lin@rock-chips.com
Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Subject: [PATCH v11 01/12] PCI: dwc: Fix EP link notification implementation
Date: Mon, 16 Jul 2018 16:52:13 +0200	[thread overview]
Message-ID: <3cefa89ce2e496e7627bd3c7ade93348230adc14.1531751641.git.gustavo.pimentel@synopsys.com> (raw)
In-Reply-To: <cover.1531751641.git.gustavo.pimentel@synopsys.com>
In-Reply-To: <cover.1531751641.git.gustavo.pimentel@synopsys.com>

Move specific features settings from EP shared code
(pcie-designware-ep.c) to the driver (pcie-designware-plat.c).

Previous implementation disables the EP link notification
by default for all SoCs that uses EP DesignWare IP, which affects
directly the dra7xx and artpec6 SoCs.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Change v8->v9:
 - Created patch file.
Change v9->v10:
 - Nothing changed, just to follow the patch set version.
Change v10->v11:
 - Missed Kishon acknowledge.

 drivers/pci/controller/dwc/pcie-designware-ep.c   | 14 ++++++--------
 drivers/pci/controller/dwc/pcie-designware-plat.c |  3 +++
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 8650416..04092a7 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -386,15 +386,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		return -ENOMEM;
 	ep->outbound_addr = addr;
 
-	if (ep->ops->ep_init)
-		ep->ops->ep_init(ep);
-
 	epc = devm_pci_epc_create(dev, &epc_ops);
 	if (IS_ERR(epc)) {
 		dev_err(dev, "Failed to create epc device\n");
 		return PTR_ERR(epc);
 	}
 
+	ep->epc = epc;
+	epc_set_drvdata(epc, ep);
+
+	if (ep->ops->ep_init)
+		ep->ops->ep_init(ep);
+
 	ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
 	if (ret < 0)
 		epc->max_functions = 1;
@@ -413,11 +416,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		return -ENOMEM;
 	}
 
-	epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER;
-	EPC_FEATURE_SET_BAR(epc->features, BAR_0);
-
-	ep->epc = epc;
-	epc_set_drvdata(epc, ep);
 	dw_pcie_setup(pci);
 
 	return 0;
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 5937fed..0ce3440 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -70,10 +70,13 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct pci_epc *epc = ep->epc;
 	enum pci_barno bar;
 
 	for (bar = BAR_0; bar <= BAR_5; bar++)
 		dw_pcie_ep_reset_bar(pci, bar);
+
+	epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
 }
 
 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
-- 
2.7.4

--
To unsubscribe from this list: send the line "unsubscribe linux-doc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

  reply	other threads:[~2018-07-16 14:52 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-16 14:52 [PATCH v11 00/12] Add MSI-X support on pcitest tool Gustavo Pimentel
2018-07-16 14:52 ` Gustavo Pimentel
2018-07-16 14:52 ` Gustavo Pimentel [this message]
2018-07-16 14:52   ` [PATCH v11 01/12] PCI: dwc: Fix EP link notification implementation Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 02/12] PCI: endpoint: Add MSI-X interfaces Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 03/12] PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 04/12] PCI: dwc: Add MSI-X callbacks handler Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 05/12] PCI: dwc: Rework MSI " Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 06/12] PCI: dwc: Add legacy interrupt callback handler Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 07/12] pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 08/12] pci-epf-test/pci_endpoint_test: Use irq_type module parameter Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 09/12] pci-epf-test/pci_endpoint_test: Add MSI-X support Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 10/12] pci_endpoint_test: Add 2 ioctl commands Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-17  2:43   ` Kishon Vijay Abraham I
2018-07-17  2:43     ` Kishon Vijay Abraham I
2018-07-17  9:33     ` Gustavo Pimentel
2018-07-17  9:33       ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 11/12] tools: PCI: Add MSI-X support Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel
2018-07-16 14:52 ` [PATCH v11 12/12] PCI: endpoint: Add MSI set maximum restriction Gustavo Pimentel
2018-07-16 14:52   ` Gustavo Pimentel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=3cefa89ce2e496e7627bd3c7ade93348230adc14.1531751641.git.gustavo.pimentel@synopsys.com \
    --to=gustavo.pimentel@synopsys.com \
    --cc=adouglas@cadence.com \
    --cc=bhelgaas@google.com \
    --cc=jesper.nilsson@axis.com \
    --cc=jingoohan1@gmail.com \
    --cc=joao.pinto@synopsys.com \
    --cc=kishon@ti.com \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=shawn.lin@rock-chips.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.