All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Summers, Stuart" <stuart.summers@intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Allow set context SSEU on platforms after gen 11
Date: Fri, 20 Sep 2019 21:10:29 +0000	[thread overview]
Message-ID: <3e0b17cb08f190b7cc1530df2d5ce386827008be.camel@intel.com> (raw)
In-Reply-To: <23b52537-1d81-eca9-87c7-ffefc1c8936e@intel.com>


[-- Attachment #1.1: Type: text/plain, Size: 1416 bytes --]

On Wed, 2019-09-18 at 13:39 -0700, Daniele Ceraolo Spurio wrote:
> 
> On 9/18/19 10:31 AM, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> > 
> 
> What's the planned usage here? TGL HW only supports slice-level 
> power-gating and with only 1 slice on TGL we don't really have a
> choice 
> of what to program, do we?

Well, we do claim powergate support on TGL, so I assumed we'd want to
enable this path. Maybe I'm missing something though. Had a similar
response to Tvrtko.

Thanks,
Stuart

> 
> Daniele
> 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index f1c0e5d958f3..39af4c81b29a 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1310,7 +1310,7 @@ static int set_sseu(struct i915_gem_context
> > *ctx,
> >   	if (args->size < sizeof(user_sseu))
> >   		return -EINVAL;
> >   
> > -	if (!IS_GEN(i915, 11))
> > +	if (INTEL_GEN(i915) < 11)
> >   		return -ENODEV;
> >   
> >   	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
> > 

[-- Attachment #1.2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3270 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-09-20 21:10 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-18 17:31 [PATCH] drm/i915: Allow set context SSEU on platforms after gen 11 Stuart Summers
2019-09-18 19:31 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-09-18 20:28   ` Summers, Stuart
2019-09-19  8:01     ` Martin Peres
2019-09-18 20:39 ` [PATCH] " Daniele Ceraolo Spurio
2019-09-20 21:10   ` Summers, Stuart [this message]
2019-09-19  7:00 ` Tvrtko Ursulin
2019-09-20 21:09   ` Summers, Stuart
2019-09-20 21:29     ` Chris Wilson
2019-09-20 21:36       ` Summers, Stuart
2019-09-23 10:34       ` Tvrtko Ursulin
2019-09-19  8:00 ` ✓ Fi.CI.IGT: success for " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=3e0b17cb08f190b7cc1530df2d5ce386827008be.camel@intel.com \
    --to=stuart.summers@intel.com \
    --cc=daniele.ceraolospurio@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.