Re: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399

From: Dragan Simic <dsimic@manjaro.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org,
	Kyle Copperfield <kmcopper@danwin1210.me>,
	conor+dt@kernel.org, robh+dt@kernel.org,
	linux-arm-kernel@lists.infradead.org,
	krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399
Date: Thu, 25 Jan 2024 23:27:56 +0100	[thread overview]
Message-ID: <4001cb956ec9603e21b31fc54007e467@manjaro.org> (raw)
In-Reply-To: <170621707730.1872080.15784453219296022164.b4-ty@sntech.de>

On 2024-01-25 22:12, Heiko Stuebner wrote:
> On Fri, 15 Dec 2023 06:00:33 +0100, Dragan Simic wrote:
>> Add missing cache information to the Rockchip RK3399 SoC dtsi.  The 
>> specified
>> values were derived by hand from the cache size specifications 
>> available from
>> the RK3399 datasheet;  for future reference, here's a brief summary:
>> 
>>   - Each Cortex-A72 core has 48 KB of L1 instruction cache and
>>     32 KB of L1 data cache available, four-way set associative
>>   - Each Cortex-A53 core core has 32 KB of instruction cache and
>>     32 KB of L1 data cache available, four-way set associative
>>   - The big (A72) cluster has 1 MB of unified L2 cache available
>>   - The little (A53) cluster has 512 KB of unified L2 cache available
>> 
>> [...]
> 
> Applied, thanks!
> 
> [1/1] arm64: dts: rockchip: Add cache information to the SoC dtsi for 
> RK3399
>       commit: b72633ba5cfa932405832de25d0f0a11716903b4

Great, thank you!