From: Vivian Wang <uwu@dram.page> To: Anup Patel <anup.patel@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bin Meng <bmeng.cn@gmail.com>, "Hongren (Zenithal) Zheng" <i@zenithal.me> Subject: Re: [RFC PATCH v4 05/10] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Date: Fri, 16 Jun 2023 22:39:09 +0800 [thread overview] Message-ID: <4440a0b1-bf67-9c37-0526-1a447ff8568a@dram.page> (raw) In-Reply-To: <20211007123632.697666-6-anup.patel@wdc.com> Hi all, We are working on devicetree generation for rocket-chip, specifically generating ACLINT nodes instead of CLINT nodes. (WIP at [1].) We were wondering if riscv,aclint-{m,s}swi should really be an interrupt-controller. According to the devicetree specification (v0.3 found at [2]), an interrupt-controller *receives* interrupts. The ACLINT devices only ever generates interrupts, so they would be classified as interrupt generating device rather than interrupt controller or interrupt nexus. These bindings, as is, require the MSWI and SSWI devices to have the interrupt-controller property and #interrupt-cells = <0>, which does not reflect its functionality. It nonsensically implies that another device may have an interrupt routed through an MSWI/SSWI as interrupt-parent. Removing these requirements makes more sense. I'm not sure about what other node name to use though. It seems that these are more like mailboxes, but also not exactly. In any case a clarification of the bindings would be appreciated. Thanks, dram [1]: https://github.com/chipsalliance/rocket-chip/pull/3330 [2]: https://www.devicetree.org/specifications/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Vivian Wang <uwu@dram.page> To: Anup Patel <anup.patel@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bin Meng <bmeng.cn@gmail.com>, "Hongren (Zenithal) Zheng" <i@zenithal.me> Subject: Re: [RFC PATCH v4 05/10] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Date: Fri, 16 Jun 2023 22:39:09 +0800 [thread overview] Message-ID: <4440a0b1-bf67-9c37-0526-1a447ff8568a@dram.page> (raw) In-Reply-To: <20211007123632.697666-6-anup.patel@wdc.com> Hi all, We are working on devicetree generation for rocket-chip, specifically generating ACLINT nodes instead of CLINT nodes. (WIP at [1].) We were wondering if riscv,aclint-{m,s}swi should really be an interrupt-controller. According to the devicetree specification (v0.3 found at [2]), an interrupt-controller *receives* interrupts. The ACLINT devices only ever generates interrupts, so they would be classified as interrupt generating device rather than interrupt controller or interrupt nexus. These bindings, as is, require the MSWI and SSWI devices to have the interrupt-controller property and #interrupt-cells = <0>, which does not reflect its functionality. It nonsensically implies that another device may have an interrupt routed through an MSWI/SSWI as interrupt-parent. Removing these requirements makes more sense. I'm not sure about what other node name to use though. It seems that these are more like mailboxes, but also not exactly. In any case a clarification of the bindings would be appreciated. Thanks, dram [1]: https://github.com/chipsalliance/rocket-chip/pull/3330 [2]: https://www.devicetree.org/specifications/
next prev parent reply other threads:[~2023-06-16 14:39 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-07 12:36 [RFC PATCH v4 00/10] Linux RISC-V ACLINT Support Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 02/10] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 03/10] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 05/10] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-08 2:46 ` Rob Herring 2021-10-08 2:46 ` Rob Herring 2021-10-08 5:46 ` Anup Patel 2021-10-08 5:46 ` Anup Patel 2023-06-16 14:39 ` Vivian Wang [this message] 2023-06-16 14:39 ` Vivian Wang 2021-10-07 12:36 ` [RFC PATCH v4 06/10] irqchip: Add ACLINT software interrupt driver Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 07/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-08 2:46 ` Rob Herring 2021-10-08 2:46 ` Rob Herring 2021-10-08 5:48 ` Anup Patel 2021-10-08 5:48 ` Anup Patel 2021-10-08 20:02 ` Rob Herring 2021-10-08 20:02 ` Rob Herring 2021-10-07 12:36 ` [RFC PATCH v4 09/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel 2021-10-07 12:36 ` Anup Patel 2021-10-07 12:36 ` [RFC PATCH v4 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel 2021-10-07 12:36 ` Anup Patel
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