All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, Nischal Varide <nischal.varide@intel.com>
Subject: [Intel-gfx] [PATCH v4 2/4] drm/i915/mso: add splitter state check
Date: Tue,  2 Mar 2021 13:03:00 +0200	[thread overview]
Message-ID: <459a332f3cdce941c57312150872559db68f88c1.1614682842.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1614682842.git.jani.nikula@intel.com>

For starters, we expect the state to be zero, as we don't enable MSO
anywhere.

v2: Refer to splitter.

Cc: Nischal Varide <nischal.varide@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 49f2a974eca2..48750435fbd6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9326,6 +9326,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
 
+	PIPE_CONF_CHECK_BOOL(splitter.enable);
+	PIPE_CONF_CHECK_I(splitter.link_count);
+	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
+
 	PIPE_CONF_CHECK_I(mst_master_transcoder);
 
 	PIPE_CONF_CHECK_BOOL(vrr.enable);
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-03-02 11:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-02 11:02 [Intel-gfx] [PATCH v4 0/4] drm/i915: complete eDP MSO support Jani Nikula
2021-03-02 11:02 ` [Intel-gfx] [PATCH v4 1/4] drm/i915/mso: add splitter state readout for platforms that support it Jani Nikula
2021-03-03 12:09   ` Shankar, Uma
2021-03-04  8:33     ` Jani Nikula
2021-03-02 11:03 ` Jani Nikula [this message]
2021-03-02 11:03 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/edp: modify fixed and downclock modes for MSO Jani Nikula
2021-03-02 11:03 ` [Intel-gfx] [PATCH v4 4/4] drm/i915/edp: enable eDP MSO during link training Jani Nikula
2021-03-02 11:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: complete eDP MSO support Patchwork
2021-03-02 12:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-03 18:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: complete eDP MSO support (rev2) Patchwork
2021-03-03 19:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-03-03 23:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: complete eDP MSO support (rev3) Patchwork
2021-03-03 23:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-04  2:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=459a332f3cdce941c57312150872559db68f88c1.1614682842.git.jani.nikula@intel.com \
    --to=jani.nikula@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=nischal.varide@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.