From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
michal.simek@xilinx.com, git@xilinx.com
Cc: Kalyani Akula <kalyani.akula@xilinx.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] arm64: dts: zynqmp: Add DisplayPort subsystem
Date: Thu, 21 Jan 2021 13:36:06 +0100 [thread overview]
Message-ID: <4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1611232558.git.michal.simek@xilinx.com>
Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Change node position and label.
---
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 +++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 22 +++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index c676afc95f6d..cf5295224750 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -231,3 +231,9 @@ &lpd_watchdog {
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
+
+&zynqmp_dpsub {
+ clocks = <&zynqmp_clk TOPSW_LSBUS>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index f12cd24adbee..a3b391d18787 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -857,5 +858,26 @@ zynqmp_dpdma: dma-controller@fd4c0000 {
clock-names = "axi_clk";
#dma-cells = <1>;
};
+
+ zynqmp_dpsub: display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+ power-domains = <&zynqmp_firmware PD_DP>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ };
};
};
--
2.30.0
WARNING: multiple messages have this Message-ID (diff)
From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
michal.simek@xilinx.com, git@xilinx.com
Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Kalyani Akula <kalyani.akula@xilinx.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] arm64: dts: zynqmp: Add DisplayPort subsystem
Date: Thu, 21 Jan 2021 13:36:06 +0100 [thread overview]
Message-ID: <4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1611232558.git.michal.simek@xilinx.com>
Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Change node position and label.
---
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 +++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 22 +++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index c676afc95f6d..cf5295224750 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -231,3 +231,9 @@ &lpd_watchdog {
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
+
+&zynqmp_dpsub {
+ clocks = <&zynqmp_clk TOPSW_LSBUS>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index f12cd24adbee..a3b391d18787 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -857,5 +858,26 @@ zynqmp_dpdma: dma-controller@fd4c0000 {
clock-names = "axi_clk";
#dma-cells = <1>;
};
+
+ zynqmp_dpsub: display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+ power-domains = <&zynqmp_firmware PD_DP>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ };
};
};
--
2.30.0
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next prev parent reply other threads:[~2021-01-21 12:38 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 12:36 [PATCH 0/3] arm64: dts: zynqmp: Enable and Wire DP Michal Simek
2021-01-21 12:36 ` Michal Simek
2021-01-21 12:36 ` [PATCH 1/3] arm64: dts: zynqmp: Add DPDMA node Michal Simek
2021-01-21 12:36 ` Michal Simek
2021-01-21 12:36 ` Michal Simek [this message]
2021-01-21 12:36 ` [PATCH 2/3] arm64: dts: zynqmp: Add DisplayPort subsystem Michal Simek
2021-01-21 12:36 ` [PATCH 3/3] arm64: dts: zynqmp: Wire up the " Michal Simek
2021-01-21 12:36 ` Michal Simek
2021-01-21 22:37 ` Laurent Pinchart
2021-01-21 22:37 ` Laurent Pinchart
2021-01-22 7:19 ` Michal Simek
2021-01-22 7:19 ` Michal Simek
2021-01-22 7:46 ` Laurent Pinchart
2021-01-22 7:46 ` Laurent Pinchart
2021-01-22 8:37 ` Michal Simek
2021-01-22 8:37 ` Michal Simek
2021-02-01 9:40 ` [PATCH 0/3] arm64: dts: zynqmp: Enable and Wire DP Michal Simek
2021-02-01 9:40 ` Michal Simek
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