[PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

From: gregory.clement@free-electrons.com (Gregory CLEMENT)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
Date: Fri, 24 Aug 2012 14:45:30 +0200	[thread overview]
Message-ID: <5037776A.6050605@free-electrons.com> (raw)
In-Reply-To: <20120824104309.GE5400@mudshark.cambridge.arm.com>

On 08/24/2012 12:43 PM, Will Deacon wrote:> On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
>> +static void __init aurora_broadcast_l2_commands(void)
>> +{
>> +       __u32 u;
>> +       /* Enable Broadcasting of cache commands to L2*/
>> +       __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
>> +       u |= 0x100;             /* Set the FW bit */
>> +       __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
>> +}
>
> Couple of questions about this code:
>
> 1. Is this register r/w from non-secure?

This register is banked.

> 2. I'm surprised that there aren't barriers and/or maintenance operations
>    needed around this operation. It might be worth checking in the
>    documentation that you have (you probably need at least an isb()
>    following the mcr).

I didn't find any mention of barriers and/or maintenance operations
needed around this operation, but maybe I have missed something, or it
was implicit for the people who wrote the documentation. I will ask
confirmation that we don't need this.

>
> Will
>
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-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com