From: William Breathitt Gray <vilhelm.gray@gmail.com>
To: jic23@kernel.org
Cc: kernel@pengutronix.de, linux-stm32@st-md-mailman.stormreply.com,
a.fatoum@pengutronix.de, kamel.bouhara@bootlin.com,
gwendal@chromium.org, alexandre.belloni@bootlin.com,
david@lechnology.com, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, syednwaris@gmail.com,
patrick.havelange@essensium.com, fabrice.gasnier@st.com,
mcoquelin.stm32@gmail.com, alexandre.torgue@st.com,
o.rempel@pengutronix.de,
William Breathitt Gray <vilhelm.gray@gmail.com>
Subject: [PATCH v10 32/33] counter: 104-quad-8: Replace mutex with spinlock
Date: Fri, 19 Mar 2021 20:00:51 +0900 [thread overview]
Message-ID: <52016584522ed9b733cd52057f6974c274e34003.1616150619.git.vilhelm.gray@gmail.com> (raw)
In-Reply-To: <cover.1616150619.git.vilhelm.gray@gmail.com>
This patch replaces the mutex I/O lock with a spinlock. This is in
preparation for a subsequent patch adding IRQ support for 104-QUAD-8
devices; we can't sleep in an interrupt context, so we'll need to use a
spinlock instead.
Cc: Syed Nayyar Waris <syednwaris@gmail.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/counter/104-quad-8.c | 90 +++++++++++++++++++++---------------
1 file changed, 53 insertions(+), 37 deletions(-)
diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c
index eb7d63769f4c..d46b8101f207 100644
--- a/drivers/counter/104-quad-8.c
+++ b/drivers/counter/104-quad-8.c
@@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
+#include <linux/spinlock.h>
#define QUAD8_EXTENT 32
@@ -28,6 +29,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
/**
* struct quad8 - device private data structure
+ * @lock: lock to prevent clobbering device states during R/W ops
* @counter: instance of the counter_device
* @fck_prescaler: array of filter clock prescaler configurations
* @preset: array of preset values
@@ -42,7 +44,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
* @base: base port address of the device
*/
struct quad8 {
- struct mutex lock;
+ spinlock_t lock;
struct counter_device counter;
unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
unsigned int preset[QUAD8_NUM_COUNTERS];
@@ -123,6 +125,7 @@ static int quad8_count_read(struct counter_device *counter,
unsigned int flags;
unsigned int borrow;
unsigned int carry;
+ unsigned long irqflags;
int i;
flags = inb(base_offset + 1);
@@ -132,7 +135,7 @@ static int quad8_count_read(struct counter_device *counter,
/* Borrow XOR Carry effectively doubles count range */
*val = (unsigned long)(borrow ^ carry) << 24;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer; transfer Counter to Output Latch */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
@@ -141,7 +144,7 @@ static int quad8_count_read(struct counter_device *counter,
for (i = 0; i < 3; i++)
*val |= (unsigned long)inb(base_offset) << (8 * i);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -151,13 +154,14 @@ static int quad8_count_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int base_offset = priv->base + 2 * count->id;
+ unsigned long irqflags;
int i;
/* Only 24-bit values are supported */
if (val > 0xFFFFFF)
return -ERANGE;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
@@ -182,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter,
/* Reset Error flag */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -200,8 +204,9 @@ static int quad8_function_read(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int id = count->id;
+ unsigned long irqflags;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
if (priv->quadrature_mode[id])
switch (priv->quadrature_scale[id]) {
@@ -218,7 +223,7 @@ static int quad8_function_read(struct counter_device *counter,
else
*function = COUNTER_FUNCTION_PULSE_DIRECTION;
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -233,10 +238,11 @@ static int quad8_function_write(struct counter_device *counter,
unsigned int *const scale = priv->quadrature_scale + id;
unsigned int *const synchronous_mode = priv->synchronous_mode + id;
const int base_offset = priv->base + 2 * id + 1;
+ unsigned long irqflags;
unsigned int mode_cfg;
unsigned int idr_cfg;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
mode_cfg = priv->count_mode[id] << 1;
idr_cfg = priv->index_polarity[id] << 1;
@@ -271,7 +277,7 @@ static int quad8_function_write(struct counter_device *counter,
break;
default:
/* should never reach this path */
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
}
@@ -279,7 +285,7 @@ static int quad8_function_write(struct counter_device *counter,
/* Load mode configuration to Counter Mode Register */
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -405,9 +411,10 @@ static int quad8_index_polarity_set(struct counter_device *counter,
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id - 16;
const int base_offset = priv->base + 2 * channel_id + 1;
+ unsigned long irqflags;
unsigned int idr_cfg = index_polarity << 1;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
idr_cfg |= priv->synchronous_mode[channel_id];
@@ -416,7 +423,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
/* Load Index Control configuration to Index Control Register */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -445,15 +452,16 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id - 16;
const int base_offset = priv->base + 2 * channel_id + 1;
+ unsigned long irqflags;
unsigned int idr_cfg = synchronous_mode;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
idr_cfg |= priv->index_polarity[channel_id] << 1;
/* Index function must be non-synchronous in non-quadrature mode */
if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
@@ -462,7 +470,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
/* Load Index Control configuration to Index Control Register */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -509,6 +517,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
unsigned int count_mode;
unsigned int mode_cfg;
const int base_offset = priv->base + 2 * count->id + 1;
+ unsigned long irqflags;
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
switch (cnt_mode) {
@@ -529,7 +538,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
return -EINVAL;
}
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->count_mode[count->id] = count_mode;
@@ -543,7 +552,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
/* Load mode configuration to Counter Mode Register */
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -563,9 +572,10 @@ static int quad8_count_enable_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int base_offset = priv->base + 2 * count->id;
+ unsigned long irqflags;
unsigned int ior_cfg;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->ab_enable[count->id] = enable;
@@ -574,7 +584,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
/* Load I/O control configuration */
outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -625,16 +635,17 @@ static int quad8_count_preset_write(struct counter_device *counter,
struct counter_count *count, u64 preset)
{
struct quad8 *const priv = counter->priv;
+ unsigned long irqflags;
/* Only 24-bit values are supported */
if (preset > 0xFFFFFF)
return -ERANGE;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
quad8_preset_register_set(priv, count->id, preset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -643,8 +654,9 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
struct counter_count *count, u64 *ceiling)
{
struct quad8 *const priv = counter->priv;
+ unsigned long irqflags;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Range Limit and Modulo-N count modes use preset value as ceiling */
switch (priv->count_mode[count->id]) {
@@ -658,7 +670,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
break;
}
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -667,23 +679,24 @@ static int quad8_count_ceiling_write(struct counter_device *counter,
struct counter_count *count, u64 ceiling)
{
struct quad8 *const priv = counter->priv;
+ unsigned long irqflags;
/* Only 24-bit values are supported */
if (ceiling > 0xFFFFFF)
return -ERANGE;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Range Limit and Modulo-N count modes use preset value as ceiling */
switch (priv->count_mode[count->id]) {
case 1:
case 3:
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
quad8_preset_register_set(priv, count->id, ceiling);
return 0;
}
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
@@ -705,12 +718,13 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int base_offset = priv->base + 2 * count->id + 1;
+ unsigned long irqflags;
unsigned int ior_cfg;
/* Preset enable is active low in Input/Output Control register */
preset_enable = !preset_enable;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->preset_enable[count->id] = preset_enable;
@@ -719,7 +733,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
/* Load I/O control configuration to Input / Output Control Register */
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -730,22 +744,23 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id / 2;
+ unsigned long irqflags;
bool disabled;
unsigned int status;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
disabled = !(priv->cable_fault_enable & BIT(channel_id));
if (disabled) {
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
/* Logic 0 = cable fault */
status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
/* Mask respective channel and invert logic */
*cable_fault = !(status & BIT(channel_id));
@@ -771,9 +786,10 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id / 2;
+ unsigned long irqflags;
unsigned int cable_fault_enable;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
if (enable)
priv->cable_fault_enable |= BIT(channel_id);
@@ -785,7 +801,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -808,8 +824,9 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id / 2;
const int base_offset = priv->base + 2 * channel_id;
+ unsigned long irqflags;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->fck_prescaler[channel_id] = prescaler;
@@ -821,7 +838,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
base_offset + 1);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -990,8 +1007,7 @@ static int quad8_probe(struct device *dev, unsigned int id)
priv->counter.priv = priv;
priv->base = base[id];
- /* Initialize mutex */
- mutex_init(&priv->lock);
+ spin_lock_init(&priv->lock);
/* Reset all counters and disable interrupt function */
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: William Breathitt Gray <vilhelm.gray@gmail.com>
To: jic23@kernel.org
Cc: kernel@pengutronix.de, linux-stm32@st-md-mailman.stormreply.com,
a.fatoum@pengutronix.de, kamel.bouhara@bootlin.com,
gwendal@chromium.org, alexandre.belloni@bootlin.com,
david@lechnology.com, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, syednwaris@gmail.com,
patrick.havelange@essensium.com, fabrice.gasnier@st.com,
mcoquelin.stm32@gmail.com, alexandre.torgue@st.com,
o.rempel@pengutronix.de,
William Breathitt Gray <vilhelm.gray@gmail.com>
Subject: [PATCH v10 32/33] counter: 104-quad-8: Replace mutex with spinlock
Date: Fri, 19 Mar 2021 20:00:51 +0900 [thread overview]
Message-ID: <52016584522ed9b733cd52057f6974c274e34003.1616150619.git.vilhelm.gray@gmail.com> (raw)
In-Reply-To: <cover.1616150619.git.vilhelm.gray@gmail.com>
This patch replaces the mutex I/O lock with a spinlock. This is in
preparation for a subsequent patch adding IRQ support for 104-QUAD-8
devices; we can't sleep in an interrupt context, so we'll need to use a
spinlock instead.
Cc: Syed Nayyar Waris <syednwaris@gmail.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/counter/104-quad-8.c | 90 +++++++++++++++++++++---------------
1 file changed, 53 insertions(+), 37 deletions(-)
diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c
index eb7d63769f4c..d46b8101f207 100644
--- a/drivers/counter/104-quad-8.c
+++ b/drivers/counter/104-quad-8.c
@@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
+#include <linux/spinlock.h>
#define QUAD8_EXTENT 32
@@ -28,6 +29,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
/**
* struct quad8 - device private data structure
+ * @lock: lock to prevent clobbering device states during R/W ops
* @counter: instance of the counter_device
* @fck_prescaler: array of filter clock prescaler configurations
* @preset: array of preset values
@@ -42,7 +44,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
* @base: base port address of the device
*/
struct quad8 {
- struct mutex lock;
+ spinlock_t lock;
struct counter_device counter;
unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
unsigned int preset[QUAD8_NUM_COUNTERS];
@@ -123,6 +125,7 @@ static int quad8_count_read(struct counter_device *counter,
unsigned int flags;
unsigned int borrow;
unsigned int carry;
+ unsigned long irqflags;
int i;
flags = inb(base_offset + 1);
@@ -132,7 +135,7 @@ static int quad8_count_read(struct counter_device *counter,
/* Borrow XOR Carry effectively doubles count range */
*val = (unsigned long)(borrow ^ carry) << 24;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer; transfer Counter to Output Latch */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
@@ -141,7 +144,7 @@ static int quad8_count_read(struct counter_device *counter,
for (i = 0; i < 3; i++)
*val |= (unsigned long)inb(base_offset) << (8 * i);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -151,13 +154,14 @@ static int quad8_count_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int base_offset = priv->base + 2 * count->id;
+ unsigned long irqflags;
int i;
/* Only 24-bit values are supported */
if (val > 0xFFFFFF)
return -ERANGE;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
@@ -182,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter,
/* Reset Error flag */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -200,8 +204,9 @@ static int quad8_function_read(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int id = count->id;
+ unsigned long irqflags;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
if (priv->quadrature_mode[id])
switch (priv->quadrature_scale[id]) {
@@ -218,7 +223,7 @@ static int quad8_function_read(struct counter_device *counter,
else
*function = COUNTER_FUNCTION_PULSE_DIRECTION;
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -233,10 +238,11 @@ static int quad8_function_write(struct counter_device *counter,
unsigned int *const scale = priv->quadrature_scale + id;
unsigned int *const synchronous_mode = priv->synchronous_mode + id;
const int base_offset = priv->base + 2 * id + 1;
+ unsigned long irqflags;
unsigned int mode_cfg;
unsigned int idr_cfg;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
mode_cfg = priv->count_mode[id] << 1;
idr_cfg = priv->index_polarity[id] << 1;
@@ -271,7 +277,7 @@ static int quad8_function_write(struct counter_device *counter,
break;
default:
/* should never reach this path */
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
}
@@ -279,7 +285,7 @@ static int quad8_function_write(struct counter_device *counter,
/* Load mode configuration to Counter Mode Register */
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -405,9 +411,10 @@ static int quad8_index_polarity_set(struct counter_device *counter,
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id - 16;
const int base_offset = priv->base + 2 * channel_id + 1;
+ unsigned long irqflags;
unsigned int idr_cfg = index_polarity << 1;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
idr_cfg |= priv->synchronous_mode[channel_id];
@@ -416,7 +423,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
/* Load Index Control configuration to Index Control Register */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -445,15 +452,16 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id - 16;
const int base_offset = priv->base + 2 * channel_id + 1;
+ unsigned long irqflags;
unsigned int idr_cfg = synchronous_mode;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
idr_cfg |= priv->index_polarity[channel_id] << 1;
/* Index function must be non-synchronous in non-quadrature mode */
if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
@@ -462,7 +470,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
/* Load Index Control configuration to Index Control Register */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -509,6 +517,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
unsigned int count_mode;
unsigned int mode_cfg;
const int base_offset = priv->base + 2 * count->id + 1;
+ unsigned long irqflags;
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
switch (cnt_mode) {
@@ -529,7 +538,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
return -EINVAL;
}
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->count_mode[count->id] = count_mode;
@@ -543,7 +552,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
/* Load mode configuration to Counter Mode Register */
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -563,9 +572,10 @@ static int quad8_count_enable_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int base_offset = priv->base + 2 * count->id;
+ unsigned long irqflags;
unsigned int ior_cfg;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->ab_enable[count->id] = enable;
@@ -574,7 +584,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
/* Load I/O control configuration */
outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -625,16 +635,17 @@ static int quad8_count_preset_write(struct counter_device *counter,
struct counter_count *count, u64 preset)
{
struct quad8 *const priv = counter->priv;
+ unsigned long irqflags;
/* Only 24-bit values are supported */
if (preset > 0xFFFFFF)
return -ERANGE;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
quad8_preset_register_set(priv, count->id, preset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -643,8 +654,9 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
struct counter_count *count, u64 *ceiling)
{
struct quad8 *const priv = counter->priv;
+ unsigned long irqflags;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Range Limit and Modulo-N count modes use preset value as ceiling */
switch (priv->count_mode[count->id]) {
@@ -658,7 +670,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
break;
}
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -667,23 +679,24 @@ static int quad8_count_ceiling_write(struct counter_device *counter,
struct counter_count *count, u64 ceiling)
{
struct quad8 *const priv = counter->priv;
+ unsigned long irqflags;
/* Only 24-bit values are supported */
if (ceiling > 0xFFFFFF)
return -ERANGE;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
/* Range Limit and Modulo-N count modes use preset value as ceiling */
switch (priv->count_mode[count->id]) {
case 1:
case 3:
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
quad8_preset_register_set(priv, count->id, ceiling);
return 0;
}
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
@@ -705,12 +718,13 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const int base_offset = priv->base + 2 * count->id + 1;
+ unsigned long irqflags;
unsigned int ior_cfg;
/* Preset enable is active low in Input/Output Control register */
preset_enable = !preset_enable;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->preset_enable[count->id] = preset_enable;
@@ -719,7 +733,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
/* Load I/O control configuration to Input / Output Control Register */
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -730,22 +744,23 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id / 2;
+ unsigned long irqflags;
bool disabled;
unsigned int status;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
disabled = !(priv->cable_fault_enable & BIT(channel_id));
if (disabled) {
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return -EINVAL;
}
/* Logic 0 = cable fault */
status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
/* Mask respective channel and invert logic */
*cable_fault = !(status & BIT(channel_id));
@@ -771,9 +786,10 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
{
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id / 2;
+ unsigned long irqflags;
unsigned int cable_fault_enable;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
if (enable)
priv->cable_fault_enable |= BIT(channel_id);
@@ -785,7 +801,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -808,8 +824,9 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
struct quad8 *const priv = counter->priv;
const size_t channel_id = signal->id / 2;
const int base_offset = priv->base + 2 * channel_id;
+ unsigned long irqflags;
- mutex_lock(&priv->lock);
+ spin_lock_irqsave(&priv->lock, irqflags);
priv->fck_prescaler[channel_id] = prescaler;
@@ -821,7 +838,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
base_offset + 1);
- mutex_unlock(&priv->lock);
+ spin_unlock_irqrestore(&priv->lock, irqflags);
return 0;
}
@@ -990,8 +1007,7 @@ static int quad8_probe(struct device *dev, unsigned int id)
priv->counter.priv = priv;
priv->base = base[id];
- /* Initialize mutex */
- mutex_init(&priv->lock);
+ spin_lock_init(&priv->lock);
/* Reset all counters and disable interrupt function */
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
--
2.30.2
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next prev parent reply other threads:[~2021-03-19 11:04 UTC|newest]
Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 11:00 [PATCH v10 00/33] Introduce the Counter character device interface William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 01/33] docs: counter: Consolidate Counter sysfs attributes documentation William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 02/33] docs: counter: Fix spelling William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 03/33] counter: 104-quad-8: Remove pointless comment William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:13 ` Syed Nayyar Waris
2021-04-15 15:13 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 04/33] counter: 104-quad-8: Return error when invalid mode during ceiling_write William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:14 ` Syed Nayyar Waris
2021-04-15 15:14 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 05/33] counter: 104-quad-8: Annotate hardware config module parameter William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:15 ` Syed Nayyar Waris
2021-04-15 15:15 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 06/33] counter: 104-quad-8: Add const qualifiers for quad8_preset_register_set William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:16 ` Syed Nayyar Waris
2021-04-15 15:16 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 07/33] counter: 104-quad-8: Add const qualifier for functions_list array William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:17 ` Syed Nayyar Waris
2021-04-15 15:17 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 08/33] counter: interrupt-cnt: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 09/33] counter: microchip-tcb-capture: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 10/33] counter: stm32-lptimer-cnt: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:22 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:22 ` Fabrice Gasnier
2021-03-19 11:00 ` [PATCH v10 11/33] counter: stm32-timer-cnt: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:22 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:22 ` Fabrice Gasnier
2021-03-19 11:00 ` [PATCH v10 12/33] counter: 104-quad-8: Add const qualifier for actions_list array William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:18 ` Syed Nayyar Waris
2021-04-15 15:18 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 13/33] counter: ftm-quaddec: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 14/33] counter: interrupt-cnt: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 15/33] counter: microchip-tcb-capture: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 16/33] counter: stm32-lptimer-cnt: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:23 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:23 ` Fabrice Gasnier
2021-03-19 11:00 ` [PATCH v10 17/33] counter: stm32-timer-cnt: " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:24 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:24 ` Fabrice Gasnier
2021-03-19 11:00 ` [PATCH v10 18/33] counter: Return error code on invalid modes William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:26 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:26 ` Fabrice Gasnier
2021-04-15 15:19 ` Syed Nayyar Waris
2021-04-15 15:19 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 19/33] counter: Standardize to ERANGE for limit exceeded errors William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:29 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:29 ` Fabrice Gasnier
2021-04-15 15:20 ` Syed Nayyar Waris
2021-04-15 15:20 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 20/33] counter: Rename counter_signal_value to counter_signal_level William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:21 ` Syed Nayyar Waris
2021-04-15 15:21 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 21/33] counter: Rename counter_count_function to counter_function William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-22 16:31 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:31 ` Fabrice Gasnier
2021-04-15 15:22 ` Syed Nayyar Waris
2021-04-15 15:22 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 22/33] counter: Internalize sysfs interface code William Breathitt Gray
2021-03-22 16:44 ` [Linux-stm32] " Fabrice Gasnier
2021-03-22 16:44 ` Fabrice Gasnier
2021-03-23 9:17 ` William Breathitt Gray
2021-03-23 9:17 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 23/33] counter: Update counter.h comments to reflect sysfs internalization William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 24/33] docs: counter: Update " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 25/33] counter: Move counter enums to uapi header William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 26/33] counter: Add character device interface William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 27/33] docs: counter: Document " William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 28/33] tools/counter: Create Counter tools William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 29/33] counter: Implement signalZ_action_component_id sysfs attribute William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 30/33] counter: Implement *_component_id sysfs attributes William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` [PATCH v10 31/33] counter: Implement events_queue_size sysfs attribute William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray [this message]
2021-03-19 11:00 ` [PATCH v10 32/33] counter: 104-quad-8: Replace mutex with spinlock William Breathitt Gray
2021-04-15 15:24 ` Syed Nayyar Waris
2021-04-15 15:24 ` Syed Nayyar Waris
2021-03-19 11:00 ` [PATCH v10 33/33] counter: 104-quad-8: Add IRQ support for the ACCES 104-QUAD-8 William Breathitt Gray
2021-03-19 11:00 ` William Breathitt Gray
2021-04-15 15:25 ` Syed Nayyar Waris
2021-04-15 15:25 ` Syed Nayyar Waris
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