From: Archit Taneja <archit@ti.com> To: Tony Lindgren <tony@atomide.com> Cc: t-kristo@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC 2/4] ARM: dts: Add ctrl-core DT node for DRA7 Date: Mon, 21 Apr 2014 10:45:28 +0530 [thread overview] Message-ID: <5354A970.8040605@ti.com> (raw) In-Reply-To: <20140418171854.GJ5354@atomide.com> Hi, On Friday 18 April 2014 10:48 PM, Tony Lindgren wrote: > * Archit Taneja <archit@ti.com> [140416 06:20]: >> Add DT node for the ctrl-core sub module of the DRA7 control module. We map the >> CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register >> fields which configure clocks. The remainder of the registers are related to >> pad configurations or cross-bar configurations, and therefore aren't mapped. > > Can you please check if this can just use the existing > regmap syscon mapping: > > syscon = <&dra7_ctrl_general>; > > See how the drivers/regulator/pbias-regulator.c is using the > syscon to initialize a regulator and then omap_hsmmc.c just does > the standard regulator calls. The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state. I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us. Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot? Archit > > Depending what the range 0x4a002000 0x6d0 contains, you may > want to set it up as another syscon area. > > Regards, > > Tony
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From: archit@ti.com (Archit Taneja) To: linux-arm-kernel@lists.infradead.org Subject: [RFC 2/4] ARM: dts: Add ctrl-core DT node for DRA7 Date: Mon, 21 Apr 2014 10:45:28 +0530 [thread overview] Message-ID: <5354A970.8040605@ti.com> (raw) In-Reply-To: <20140418171854.GJ5354@atomide.com> Hi, On Friday 18 April 2014 10:48 PM, Tony Lindgren wrote: > * Archit Taneja <archit@ti.com> [140416 06:20]: >> Add DT node for the ctrl-core sub module of the DRA7 control module. We map the >> CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register >> fields which configure clocks. The remainder of the registers are related to >> pad configurations or cross-bar configurations, and therefore aren't mapped. > > Can you please check if this can just use the existing > regmap syscon mapping: > > syscon = <&dra7_ctrl_general>; > > See how the drivers/regulator/pbias-regulator.c is using the > syscon to initialize a regulator and then omap_hsmmc.c just does > the standard regulator calls. The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state. I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us. Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot? Archit > > Depending what the range 0x4a002000 0x6d0 contains, you may > want to set it up as another syscon area. > > Regards, > > Tony
next prev parent reply other threads:[~2014-04-21 5:16 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-04-16 13:14 [RFC 1/4] ARM: OMAP2+: Add CTRL_MODULE_CORE as a master clock provider for DRA7 Archit Taneja 2014-04-16 13:14 ` Archit Taneja 2014-04-16 13:14 ` [RFC 2/4] ARM: dts: Add ctrl-core DT node " Archit Taneja 2014-04-16 13:14 ` Archit Taneja 2014-04-18 17:18 ` Tony Lindgren 2014-04-18 17:18 ` Tony Lindgren 2014-04-21 5:15 ` Archit Taneja [this message] 2014-04-21 5:15 ` Archit Taneja 2014-04-21 15:10 ` Tony Lindgren 2014-04-21 15:10 ` Tony Lindgren 2014-05-06 5:22 ` Archit Taneja 2014-05-06 5:22 ` Archit Taneja 2014-05-06 14:26 ` Tony Lindgren 2014-05-06 14:26 ` Tony Lindgren 2014-05-08 6:02 ` Archit Taneja 2014-05-08 6:02 ` Archit Taneja 2014-05-08 7:53 ` Tero Kristo 2014-05-08 7:53 ` Tero Kristo 2014-05-08 8:16 ` Archit Taneja 2014-05-08 8:16 ` Archit Taneja 2014-04-16 13:14 ` [RFC 3/4] ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core Archit Taneja 2014-04-16 13:14 ` Archit Taneja 2014-04-16 13:14 ` [RFC 4/4] CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init Archit Taneja 2014-04-16 13:14 ` Archit Taneja 2014-05-08 1:19 ` [RFC 1/4] ARM: OMAP2+: Add CTRL_MODULE_CORE as a master clock provider for DRA7 Paul Walmsley 2014-05-08 1:19 ` Paul Walmsley 2014-05-28 10:50 ` [RFC v2 0/6] ARM: dts: Add a new clk provider, and implement dss_deshdcp clock with it Archit Taneja 2014-05-28 10:50 ` [RFC v2 1/6] CLK: TI: clockdomain: add support for retrying init Archit Taneja 2014-05-28 10:50 ` [RFC v2 2/6] ARM: PRCM: split PRCM module init to their own driver files Archit Taneja 2014-06-16 11:48 ` Tony Lindgren 2014-05-28 10:50 ` [RFC v2 3/6] ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x Archit Taneja 2014-05-28 10:50 ` [RFC v2 4/6] ARM: dts: Add ctrl-core DT node for DRA7 Archit Taneja 2014-05-28 10:50 ` [RFC v2 5/6] ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core Archit Taneja 2014-05-28 10:50 ` [RFC v2 6/6] CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init Archit Taneja
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