All of lore.kernel.org
 help / color / mirror / Atom feed
From: Thor Thayer <tthayer@opensource.altera.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: broonie@kernel.org, grant.likely@linaro.org, jkosina@suse.cz,
	pawel.moll@arm.com, robh+dt@kernel.org, mark.rutland@arm.com,
	ijc+devicetree@hellion.org.uk, dinguyen@opensource.altera.com,
	linux-doc@vger.kernel.org, linux-spi@vger.kernel.org,
	devicetree@vger.kernel.org, tthayer.linux@gmail.com,
	axel.lin@ingics.com, baruch@tkos.co.il, jg1.han@samsung.com,
	galak@codeaurora.org
Subject: Re: [RFC/PATCH 0/2] spi: spi-dw: Select 16b or 32b register access
Date: Wed, 4 Mar 2015 16:01:02 -0600	[thread overview]
Message-ID: <54F7809E.2010307@opensource.altera.com> (raw)
In-Reply-To: <1425501868.14897.178.camel@linux.intel.com>

Hi Andy,

On 03/04/2015 02:44 PM, Andy Shevchenko wrote:
> On Wed, 2015-03-04 at 14:31 -0600, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> The Altera Arria10 SoC requires 32 bit accesses to peripherals. The
>> DesignWare SPI peripheral registers are on 32bit boundaries so this
>> patch is minimal. Function pointers are used to select 32bit access
>> or 16bit accesses.
>
>
> So, what is exactly the issue when we read only half of the register?
> Bus lock, or what?
>

The read actually works on our chip but I changed both read and write to 
be consistent. For Arria10, on a 16 bit write the data isn't written 
into the DesignWare register.

In reply to your other email, yes it does support the DW_apb_ssi but the 
Arria10 architecture requires 32 bit access (actually as you point out, 
32 bit writes). We're using the original driver on our older chips but 
Arria10 requires upstream changes.

>>
>> Thor Thayer (2):
>>    dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI
>>    spi: dw-spi: Pointers select 16b vs. 32b DesignWare access
>>
>>   Documentation/devicetree/bindings/spi/spi-dw.txt |    1 +
>>   drivers/spi/spi-dw-mmio.c                        |    7 +++-
>>   drivers/spi/spi-dw.c                             |   38 +++++++++++++---------
>>   drivers/spi/spi-dw.h                             |   10 +++---
>>   4 files changed, 35 insertions(+), 21 deletions(-)
>>
>
>

WARNING: multiple messages have this Message-ID (diff)
From: Thor Thayer <tthayer@opensource.altera.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: <broonie@kernel.org>, <grant.likely@linaro.org>,
	<jkosina@suse.cz>, <pawel.moll@arm.com>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>, <ijc+devicetree@hellion.org.uk>,
	<dinguyen@opensource.altera.com>, <linux-doc@vger.kernel.org>,
	<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<tthayer.linux@gmail.com>, <axel.lin@ingics.com>,
	<baruch@tkos.co.il>, <jg1.han@samsung.com>,
	<galak@codeaurora.org>
Subject: Re: [RFC/PATCH 0/2] spi: spi-dw: Select 16b or 32b register access
Date: Wed, 4 Mar 2015 16:01:02 -0600	[thread overview]
Message-ID: <54F7809E.2010307@opensource.altera.com> (raw)
In-Reply-To: <1425501868.14897.178.camel@linux.intel.com>

Hi Andy,

On 03/04/2015 02:44 PM, Andy Shevchenko wrote:
> On Wed, 2015-03-04 at 14:31 -0600, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> The Altera Arria10 SoC requires 32 bit accesses to peripherals. The
>> DesignWare SPI peripheral registers are on 32bit boundaries so this
>> patch is minimal. Function pointers are used to select 32bit access
>> or 16bit accesses.
>
>
> So, what is exactly the issue when we read only half of the register?
> Bus lock, or what?
>

The read actually works on our chip but I changed both read and write to 
be consistent. For Arria10, on a 16 bit write the data isn't written 
into the DesignWare register.

In reply to your other email, yes it does support the DW_apb_ssi but the 
Arria10 architecture requires 32 bit access (actually as you point out, 
32 bit writes). We're using the original driver on our older chips but 
Arria10 requires upstream changes.

>>
>> Thor Thayer (2):
>>    dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI
>>    spi: dw-spi: Pointers select 16b vs. 32b DesignWare access
>>
>>   Documentation/devicetree/bindings/spi/spi-dw.txt |    1 +
>>   drivers/spi/spi-dw-mmio.c                        |    7 +++-
>>   drivers/spi/spi-dw.c                             |   38 +++++++++++++---------
>>   drivers/spi/spi-dw.h                             |   10 +++---
>>   4 files changed, 35 insertions(+), 21 deletions(-)
>>
>
>

  reply	other threads:[~2015-03-04 22:01 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-04 20:31 [RFC/PATCH 0/2] spi: spi-dw: Select 16b or 32b register access tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-04 20:31 ` tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
     [not found] ` <1425501075-17081-1-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-04 20:31   ` [RFC/PATCH 1/2] dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-04 20:31     ` tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-04 20:44   ` [RFC/PATCH 0/2] spi: spi-dw: Select 16b or 32b register access Andy Shevchenko
2015-03-04 22:01     ` Thor Thayer [this message]
2015-03-04 22:01       ` Thor Thayer
     [not found]       ` <54F7809E.2010307-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-05 10:43         ` Andy Shevchenko
     [not found]           ` <1425552233.14897.189.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-05 20:41             ` Thor Thayer
2015-03-05 20:41               ` Thor Thayer
2015-03-05 21:54               ` Andy Shevchenko
2015-03-06 23:06                 ` Thor Thayer
2015-03-06 23:06                   ` Thor Thayer
2015-03-04 20:31 ` [RFC/PATCH 2/2] spi: dw-spi: Pointers select 16b vs. 32b DesignWare access tthayer
2015-03-04 20:31   ` tthayer
2015-03-04 20:55   ` Andy Shevchenko
     [not found]     ` <1425502525.14897.185.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-04 22:07       ` Thor Thayer
2015-03-04 22:07         ` Thor Thayer
2015-03-04 21:02 ` [RFC/PATCH 0/2] spi: spi-dw: Select 16b or 32b register access Andy Shevchenko

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=54F7809E.2010307@opensource.altera.com \
    --to=tthayer@opensource.altera.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=axel.lin@ingics.com \
    --cc=baruch@tkos.co.il \
    --cc=broonie@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dinguyen@opensource.altera.com \
    --cc=galak@codeaurora.org \
    --cc=grant.likely@linaro.org \
    --cc=ijc+devicetree@hellion.org.uk \
    --cc=jg1.han@samsung.com \
    --cc=jkosina@suse.cz \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-spi@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=pawel.moll@arm.com \
    --cc=robh+dt@kernel.org \
    --cc=tthayer.linux@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.