Re: [PATCH v7 1/4] Documentation: dt-bindings: Describe SROMc configuration

From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
To: Rob Herring <robh+dt@kernel.org>, Pavel Fedin <p.fedin@samsung.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-samsung-soc@vger.kernel.org" 
	<linux-samsung-soc@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>, Kukjin Kim <kgene@kernel.org>
Subject: Re: [PATCH v7 1/4] Documentation: dt-bindings: Describe SROMc configuration
Date: Thu, 12 Nov 2015 09:32:10 +0900	[thread overview]
Message-ID: <5643DE0A.2060400@samsung.com> (raw)
In-Reply-To: <CAL_JsqLtWwdGHKKfS8b6E0Urh6gYopZcwpdyvJGWCRm7x81YzA@mail.gmail.com>

On 12.11.2015 05:43, Rob Herring wrote:
> On Wed, Nov 11, 2015 at 12:44 AM, Pavel Fedin <p.fedin@samsung.com> wrote:
>>  Hello!
>>
>>>> +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
>>>> +                        following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
>>>> +                        Each value is specified in cycles and has the following
>>>> +                        meaning and valid range:
>>>> +                        Tacp : Page mode access cycle at Page mode (0 - 15)
>>>> +                        Tcah : Address holding time after CSn (0 - 15)
>>>> +                        Tcoh : Chip selection hold on OEn (0 - 15)
>>>> +                        Tacc : Access cycle (0 - 31, the actual time is N + 1)
>>>> +                        Tcos : Chip selection set-up before OEn (0 - 15)
>>>> +                        Tacs : Address set-up before CSn (0 - 15)
>>>
>>> This is not easily extended. Perhaps a property per value instead.
>>
>>  We had a discussion with Krzysztof about it, he agreed with this form of the property.
>> My concern was that it's just too much typing, and makes little sense because these
>> settings always go together. If register layout changes, or parameter set changes in
>> incompatible way, then it's another device, not exynos-srom anymore.
>>  So would you agree with that, or is your position strong?
> 
> I'm thinking for a new version of the controller which could add (or
> remove) new timing parameters, but then I guess you can interpret the
> field differently based on the compatible string. Anyway, your problem
> to deal with.

Actually I also preferred properties per one timing... but finally
agreed on simpler approach.

Adding new parameters to the array is still possible (because the order
matters) and removal as well (by ignoring some indices). All ARMv7
Exynos SoCs have exactly the same registers for SROM controller
(Exynos3250, Exynos4, Exynos5). On newer Exynos ARMv8 (Exynos5433 and
Exynos7420) I don't know because it is not documented.

Best regards,
Krzysztof