Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation. - Jean-Christophe DUBOIS

From: Jean-Christophe DUBOIS <jcd@tribudubois.net>
To: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.
Date: Sun, 21 Feb 2016 14:42:00 +0100	[thread overview]
Message-ID: <56C9BEA8.2080306@tribudubois.net> (raw)
In-Reply-To: <CAPokK=pA5vLp_An5ZTN-GP+A69otxRqSc+bomsDYuMmJTxJeSg@mail.gmail.com>

Le 21/02/2016 04:42, Peter Crosthwaite a écrit :
> On Sat, Feb 20, 2016 at 10:03 AM, Jean-Christophe DUBOIS
> <jcd@tribudubois.net> wrote:
>> Le 20/02/2016 16:30, Peter Crosthwaite a écrit :
>>> On Sat, Feb 20, 2016 at 2:55 AM, Jean-Christophe DUBOIS
>>> <jcd@tribudubois.net> wrote:
>>>> Just to compare I tried to run Linux on QEMU emulating highbank.
>>>>
>>>> For now I am unable to start in SMP mode. Only one core is activated.
>>>>
>>> This is probably due to the fact that the PSCI command encodings for
>>> Highbank expected by the kernel are mismatched to the ones in QEMU. I
>>> had some patches to change them, but once I got the PSCI right, the
>>> boot hung (might be just extreme slowdown like you describe) and I
>>> never got the time to fully debug it. SO there is a good chance
>>> Highbank has the same bug.
>>
>> Thanks Peter,
>>
>> So we are not sure we have a reference Cortex A9 platform working with
>> has_el3 set to true.
>>
> Not for SMP linux.

And do we have other 32 bits Cortex (A5/A7/A15/...) that support has_el3 
in SMP?

JC

>
> Regards,
> Peter
>
>> This is annoying.
>>
>> JC
>>
>>> Regards,
>>> Peter
>>>