From: Chris Zhong <zyw@rock-chips.com>
To: John Keeping <john@metanate.com>, Mark Yao <mark.yao@rock-chips.com>
Cc: dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured
Date: Sun, 22 Jan 2017 18:07:38 +0800 [thread overview]
Message-ID: <5884846A.7040200@rock-chips.com> (raw)
In-Reply-To: <20170121163128.22240-18-john@metanate.com>
Hi John
This patch do the similar thing with
https://patchwork.kernel.org/patch/9530405/
They are changing the phy configuration order, my suggestion is to merge
them.
On 01/22/2017 12:31 AM, John Keeping wrote:
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v2
> ---
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index ce1e6f9a2041..cfe7e4ba305c 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -413,12 +413,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>
> dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
>
> - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
> dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
> LOW_PROGRAM_EN);
> dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
> HIGH_PROGRAM_EN);
> + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
>
> dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> BIASEXTR_SEL(BIASEXTR_127_7));
WARNING: multiple messages have this Message-ID (diff)
From: Chris Zhong <zyw@rock-chips.com>
To: John Keeping <john@metanate.com>, Mark Yao <mark.yao@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured
Date: Sun, 22 Jan 2017 18:07:38 +0800 [thread overview]
Message-ID: <5884846A.7040200@rock-chips.com> (raw)
In-Reply-To: <20170121163128.22240-18-john@metanate.com>
Hi John
This patch do the similar thing with
https://patchwork.kernel.org/patch/9530405/
They are changing the phy configuration order, my suggestion is to merge
them.
On 01/22/2017 12:31 AM, John Keeping wrote:
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v2
> ---
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index ce1e6f9a2041..cfe7e4ba305c 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -413,12 +413,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>
> dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
>
> - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
> dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
> LOW_PROGRAM_EN);
> dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
> HIGH_PROGRAM_EN);
> + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
>
> dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> BIASEXTR_SEL(BIASEXTR_127_7));
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WARNING: multiple messages have this Message-ID (diff)
From: zyw@rock-chips.com (Chris Zhong)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured
Date: Sun, 22 Jan 2017 18:07:38 +0800 [thread overview]
Message-ID: <5884846A.7040200@rock-chips.com> (raw)
In-Reply-To: <20170121163128.22240-18-john@metanate.com>
Hi John
This patch do the similar thing with
https://patchwork.kernel.org/patch/9530405/
They are changing the phy configuration order, my suggestion is to merge
them.
On 01/22/2017 12:31 AM, John Keeping wrote:
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v2
> ---
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index ce1e6f9a2041..cfe7e4ba305c 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -413,12 +413,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>
> dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
>
> - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
> dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
> LOW_PROGRAM_EN);
> dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
> HIGH_PROGRAM_EN);
> + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
>
> dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> BIASEXTR_SEL(BIASEXTR_127_7));
next prev parent reply other threads:[~2017-01-22 10:10 UTC|newest]
Thread overview: 143+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-21 16:31 [PATCH v2 00/26] drm/rockchip: MIPI fixes & improvements John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 3:58 ` Chris Zhong
2017-01-22 3:58 ` Chris Zhong
2017-01-22 3:58 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 02/26] drm/rockchip: dw-mipi-dsi: rename commit hook to enable John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 4:00 ` Chris Zhong
2017-01-22 4:00 ` Chris Zhong
2017-01-22 4:00 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 6:08 ` Chris Zhong
2017-01-22 6:08 ` Chris Zhong
2017-01-22 6:08 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 05/26] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 6:24 ` Chris Zhong
2017-01-22 6:24 ` Chris Zhong
2017-01-22 6:24 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 6:42 ` Chris Zhong
2017-01-22 6:42 ` Chris Zhong
2017-01-22 6:42 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 6:44 ` Chris Zhong
2017-01-22 6:44 ` Chris Zhong
2017-01-22 6:44 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 09/26] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 7:14 ` Chris Zhong
2017-01-22 7:14 ` Chris Zhong
2017-01-22 7:14 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 8:10 ` Chris Zhong
2017-01-22 8:10 ` Chris Zhong
2017-01-22 8:10 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 11/26] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 8:16 ` Chris Zhong
2017-01-22 8:16 ` Chris Zhong
2017-01-22 8:16 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 12/26] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 8:22 ` Chris Zhong
2017-01-22 8:22 ` Chris Zhong
2017-01-22 8:22 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 13/26] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 8:37 ` Chris Zhong
2017-01-22 8:37 ` Chris Zhong
2017-01-22 8:37 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 9:37 ` Chris Zhong
2017-01-22 9:37 ` Chris Zhong
2017-01-22 9:37 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 9:37 ` Chris Zhong
2017-01-22 9:37 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 16/26] drm/rockchip: dw-mipi-dsi: configure bias and bandgap before enable John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 10:07 ` Chris Zhong [this message]
2017-01-22 10:07 ` Chris Zhong
2017-01-22 10:07 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 3:06 ` Chris Zhong
2017-01-22 3:06 ` Chris Zhong
2017-01-22 3:06 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-23 1:38 ` Chris Zhong
2017-01-23 1:38 ` Chris Zhong
2017-01-23 1:38 ` Chris Zhong
2017-01-23 12:49 ` John Keeping
2017-01-23 12:49 ` John Keeping
2017-01-23 12:49 ` John Keeping
2017-01-24 2:42 ` Chris Zhong
2017-01-24 2:42 ` Chris Zhong
2017-01-24 2:42 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-23 0:49 ` Chris Zhong
2017-01-23 0:49 ` Chris Zhong
2017-01-23 0:49 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 21/26] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC John Keeping
2017-01-21 16:31 ` [PATCH v2 21/26] drm/rockchip: dw-mipi-dsi: use positive check for N{H, V}SYNC John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` [PATCH v2 22/26] drm/rockchip: vop: test for P{H,V}SYNC John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-23 7:12 ` Mark yao
2017-01-23 7:12 ` Mark yao
2017-01-21 16:31 ` [PATCH v2 23/26] drm/rockchip: dw-mipi-dsi: defer probe if panel is not loaded John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` [PATCH v2 24/26] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-23 6:11 ` Chris Zhong
2017-01-23 6:11 ` Chris Zhong
2017-01-23 6:11 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-23 6:12 ` Chris Zhong
2017-01-23 6:12 ` Chris Zhong
2017-01-21 16:31 ` [PATCH v2 26/26] drm/rockchip: dw-mipi-dsi: support read commands John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-21 16:31 ` John Keeping
2017-01-22 3:08 ` Chris Zhong
2017-01-22 3:08 ` Chris Zhong
2017-01-22 3:08 ` Chris Zhong
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