From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, Chanwoo Choi <cw00.choi@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "MyungJoo Ham" <myungjoo.ham@samsung.com>, "Kyungmin Park" <kyungmin.park@samsung.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Shawn Guo" <shawnguo@kernel.org>, "Mark Rutland" <mark.rutland@arm.com>, "Michael Turquette" <mturquette@baylibre.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Saravana Kannan" <saravanak@google.com>, "Angus Ainslie" <angus@akkea.ca>, "Martin Kepplinger" <martink@posteo.de>, "Matthias Kaehlcke" <mka@chromium.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Alexandre Bailon" <abailon@baylibre.com>, "Georgi Djakov" <georgi.djakov@linaro.org>, "Dong Aisheng" <aisheng.dong@nxp.com>, "Abel Vesa" <abel.vesa@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Fabio Estevam" <fabio.estevam@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "Silvano di Ninno" <silvano.dininno@nxp.com>, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller Date: Fri, 22 Nov 2019 23:45:02 +0200 [thread overview] Message-ID: <5b2f8980c471e1a8a9a3307903829fe015fd4b6c.1574458460.git.leonard.crestez@nxp.com> (raw) In-Reply-To: <cover.1574458460.git.leonard.crestez@nxp.com> In-Reply-To: <cover.1574458460.git.leonard.crestez@nxp.com> Add devicetree bindings for the i.MX DDR Controller on imx8m series chips. It supports dynamic frequency switching between multiple data rates and this is exposed to Linux via the devfreq subsystem. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../memory-controllers/fsl/imx8m-ddrc.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml new file mode 100644 index 000000000000..c9e6c22cb5be --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8M DDR Controller + +maintainers: + - Leonard Crestez <leonard.crestez@nxp.com> + +description: + The DDRC block is integrated in i.MX8M for interfacing with DDR based + memories. + + It supports switching between different frequencies at runtime but during + this process RAM itself becomes briefly inaccessible so actual frequency + switching is implemented by TF-A code which runs from a SRAM area. + + The Linux driver for the DDRC doesn't even map registers (they're included + for the sake of "describing hardware"), it mostly just exposes firmware + capabilities through standard Linux mechanism like devfreq and OPP tables. + +properties: + compatible: + items: + - enum: + - fsl,imx8mn-ddrc + - fsl,imx8mm-ddrc + - fsl,imx8mq-ddrc + - const: fsl,imx8m-ddrc + + reg: + maxItems: 1 + description: + Base address and size of DDRC CTL area. + This is not currently mapped by the imx8m-ddrc driver. + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pll + - const: alt + - const: apb + + operating-points-v2: true + opp-table: true + +required: + - reg + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + operating-points-v2 = <&ddrc_opp_table>; + }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Leonard Crestez <leonard.crestez@nxp.com> To: Stephen Boyd <sboyd@kernel.org>, Chanwoo Choi <cw00.choi@samsung.com>, Rob Herring <robh+dt@kernel.org> Cc: "Mark Rutland" <mark.rutland@arm.com>, "Artur Świgoń" <a.swigon@partner.samsung.com>, "Jacky Bai" <ping.bai@nxp.com>, "Viresh Kumar" <viresh.kumar@linaro.org>, "Michael Turquette" <mturquette@baylibre.com>, "Angus Ainslie" <angus@akkea.ca>, "Alexandre Bailon" <abailon@baylibre.com>, "Matthias Kaehlcke" <mka@chromium.org>, "Abel Vesa" <abel.vesa@nxp.com>, "Saravana Kannan" <saravanak@google.com>, "Krzysztof Kozlowski" <krzk@kernel.org>, linux-clk@vger.kernel.org, "MyungJoo Ham" <myungjoo.ham@samsung.com>, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, "Martin Kepplinger" <martink@posteo.de>, "Silvano di Ninno" <silvano.dininno@nxp.com>, linux-arm-kernel@lists.infradead.org, "Dong Aisheng" <aisheng.dong@nxp.com>, "Anson Huang" <Anson.Huang@nxp.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, "Kyungmin Park" <kyungmin.park@samsung.com>, kernel@pengutronix.de, "Fabio Estevam" <fabio.estevam@nxp.com>, "Shawn Guo" <shawnguo@kernel.org>, "Georgi Djakov" <georgi.djakov@linaro.org> Subject: [PATCH v7 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller Date: Fri, 22 Nov 2019 23:45:02 +0200 [thread overview] Message-ID: <5b2f8980c471e1a8a9a3307903829fe015fd4b6c.1574458460.git.leonard.crestez@nxp.com> (raw) In-Reply-To: <cover.1574458460.git.leonard.crestez@nxp.com> In-Reply-To: <cover.1574458460.git.leonard.crestez@nxp.com> Add devicetree bindings for the i.MX DDR Controller on imx8m series chips. It supports dynamic frequency switching between multiple data rates and this is exposed to Linux via the devfreq subsystem. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../memory-controllers/fsl/imx8m-ddrc.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml new file mode 100644 index 000000000000..c9e6c22cb5be --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8M DDR Controller + +maintainers: + - Leonard Crestez <leonard.crestez@nxp.com> + +description: + The DDRC block is integrated in i.MX8M for interfacing with DDR based + memories. + + It supports switching between different frequencies at runtime but during + this process RAM itself becomes briefly inaccessible so actual frequency + switching is implemented by TF-A code which runs from a SRAM area. + + The Linux driver for the DDRC doesn't even map registers (they're included + for the sake of "describing hardware"), it mostly just exposes firmware + capabilities through standard Linux mechanism like devfreq and OPP tables. + +properties: + compatible: + items: + - enum: + - fsl,imx8mn-ddrc + - fsl,imx8mm-ddrc + - fsl,imx8mq-ddrc + - const: fsl,imx8m-ddrc + + reg: + maxItems: 1 + description: + Base address and size of DDRC CTL area. + This is not currently mapped by the imx8m-ddrc driver. + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pll + - const: alt + - const: apb + + operating-points-v2: true + opp-table: true + +required: + - reg + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + operating-points-v2 = <&ddrc_opp_table>; + }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-22 21:45 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-22 21:44 [PATCH v7 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez 2019-11-22 21:44 ` Leonard Crestez 2019-11-22 21:45 ` [PATCH v7 1/5] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez 2019-11-22 21:45 ` Leonard Crestez 2019-11-25 1:25 ` Stephen Boyd 2019-12-09 1:15 ` Shawn Guo 2019-12-09 1:15 ` Shawn Guo 2019-11-22 21:45 ` [PATCH v7 2/5] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez 2019-11-22 21:45 ` Leonard Crestez 2019-11-25 1:26 ` Stephen Boyd 2019-12-09 1:16 ` Shawn Guo 2019-12-09 1:16 ` Shawn Guo 2019-11-22 21:45 ` Leonard Crestez [this message] 2019-11-22 21:45 ` [PATCH v7 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez 2019-11-22 21:45 ` [PATCH v7 4/5] PM / devfreq: Add dynamic scaling " Leonard Crestez 2019-11-22 21:45 ` Leonard Crestez 2019-11-24 23:59 ` Chanwoo Choi 2019-11-24 23:59 ` Chanwoo Choi 2019-11-26 19:44 ` Rob Herring 2019-11-26 19:44 ` Rob Herring 2019-11-26 23:25 ` Chanwoo Choi 2019-11-26 23:25 ` Chanwoo Choi [not found] ` <CGME20191219230258epcas1p16ec64c3a06eafd9f0a3784d18541ce5c@epcas1p1.samsung.com> 2019-12-19 23:09 ` [v8 PATCH] " Chanwoo Choi 2019-12-19 23:10 ` Chanwoo Choi 2019-11-22 21:45 ` [PATCH v7 5/5] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez 2019-11-22 21:45 ` Leonard Crestez 2019-11-28 14:43 ` Adam Ford 2019-11-28 14:43 ` Adam Ford 2019-11-29 5:33 ` Leonard Crestez 2019-11-29 5:33 ` Leonard Crestez 2019-12-09 1:34 ` Shawn Guo 2019-12-09 1:34 ` Shawn Guo 2019-12-18 13:35 ` [PATCH v7 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Adam Ford 2019-12-18 13:35 ` Adam Ford 2019-12-18 14:44 ` Leonard Crestez 2019-12-18 14:44 ` Leonard Crestez 2019-12-18 15:05 ` Adam Ford 2019-12-18 15:05 ` Adam Ford 2019-12-18 15:16 ` Leonard Crestez 2019-12-18 15:16 ` Leonard Crestez 2019-12-18 15:37 ` Adam Ford 2019-12-18 15:37 ` Adam Ford 2019-12-18 16:22 ` Leonard Crestez 2019-12-18 16:22 ` Leonard Crestez 2019-12-18 16:42 ` Adam Ford 2019-12-18 16:42 ` Adam Ford [not found] ` <CAHCN7xKjpN_XEGLj-1jMG5mBbF=su67k+10frheLt+L1XaR0-g@mail.gmail.com> 2020-01-13 23:36 ` Leonard Crestez 2020-01-13 23:36 ` Leonard Crestez 2020-01-15 20:09 ` Adam Ford 2020-01-15 20:09 ` Adam Ford
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