From: "Gupta, Anshuman" <anshuman.gupta@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: linux-hwmon@vger.kernel.org, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power
Date: Thu, 22 Sep 2022 10:54:12 +0530 [thread overview]
Message-ID: <5c88044c-7ad6-80aa-634b-139532f9bf59@intel.com> (raw)
In-Reply-To: <87fsgkm71w.wl-ashutosh.dixit@intel.com>
On 9/22/2022 8:47 AM, Dixit, Ashutosh wrote:
> On Wed, 21 Sep 2022 08:07:15 -0700, Gupta, Anshuman wrote:
>>
>
> Hi Anshuman,
>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 55c35903adca..956e5298ef1e 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6644,6 +6644,12 @@
>>> #define DG1_PCODE_STATUS 0x7E
>>> #define DG1_UNCORE_GET_INIT_STATUS 0x0
>>> #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
>>> +#define PCODE_POWER_SETUP 0x7C
>>> +#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
>>> +#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
>>> +#define POWER_SETUP_I1_WATTS REG_BIT(31)
>>> +#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
>> Could please add some comment to explain, why POWER_SETUP_I1_SHIFT = 6,
>> what is excatly 10.6 fixed point format ?
>> With that.
>> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> 10.6 fixed point format means a 16 bit number is represented as x.y where x
> are the top 10 bits and y are the bottom 6 bits. The float value of this 16
> bit number is (x + (y / 2^6)), so (x + (y / 64)). For example the number
> 0x8008 will have the value (1 * 2^9 + 8 / 2^6) == 512.125. Note that the
> hexadecimal number 0x8008 == 32776 and 512.125 == 32776 / 64 which is why
> POWER_SETUP_I1_SHIFT is 6 (2^6 == 64).
>
> Similarly, the 8.8 fixed point format is explained in
> gt/intel_gt_sysfs_pm.c. Do you think this needs a comment? I thought "10.6
> fixed point format" is a sufficient hint (fixed point numbers are fairly
> well known).
>
> An even trickier data format is in the patch "drm/i915/hwmon: Expose
> power1_max_interval" in hwm_power1_max_interval_show() but I think I have a
> long comment there.
Thanks for explaining this, i was unaware of fixed point representation.
My RB can can be used without any change.
Br,
Anshuman.
>
> Thanks.
> --
> Ashutosh
WARNING: multiple messages have this Message-ID (diff)
From: "Gupta, Anshuman" <anshuman.gupta@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: Badal Nilawar <badal.nilawar@intel.com>,
<intel-gfx@lists.freedesktop.org>, <riana.tauro@intel.com>,
<jon.ewins@intel.com>, <linux-hwmon@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power
Date: Thu, 22 Sep 2022 10:54:12 +0530 [thread overview]
Message-ID: <5c88044c-7ad6-80aa-634b-139532f9bf59@intel.com> (raw)
In-Reply-To: <87fsgkm71w.wl-ashutosh.dixit@intel.com>
On 9/22/2022 8:47 AM, Dixit, Ashutosh wrote:
> On Wed, 21 Sep 2022 08:07:15 -0700, Gupta, Anshuman wrote:
>>
>
> Hi Anshuman,
>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 55c35903adca..956e5298ef1e 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6644,6 +6644,12 @@
>>> #define DG1_PCODE_STATUS 0x7E
>>> #define DG1_UNCORE_GET_INIT_STATUS 0x0
>>> #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
>>> +#define PCODE_POWER_SETUP 0x7C
>>> +#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
>>> +#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
>>> +#define POWER_SETUP_I1_WATTS REG_BIT(31)
>>> +#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
>> Could please add some comment to explain, why POWER_SETUP_I1_SHIFT = 6,
>> what is excatly 10.6 fixed point format ?
>> With that.
>> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> 10.6 fixed point format means a 16 bit number is represented as x.y where x
> are the top 10 bits and y are the bottom 6 bits. The float value of this 16
> bit number is (x + (y / 2^6)), so (x + (y / 64)). For example the number
> 0x8008 will have the value (1 * 2^9 + 8 / 2^6) == 512.125. Note that the
> hexadecimal number 0x8008 == 32776 and 512.125 == 32776 / 64 which is why
> POWER_SETUP_I1_SHIFT is 6 (2^6 == 64).
>
> Similarly, the 8.8 fixed point format is explained in
> gt/intel_gt_sysfs_pm.c. Do you think this needs a comment? I thought "10.6
> fixed point format" is a sufficient hint (fixed point numbers are fairly
> well known).
>
> An even trickier data format is in the patch "drm/i915/hwmon: Expose
> power1_max_interval" in hwm_power1_max_interval_show() but I think I have a
> long comment there.
Thanks for explaining this, i was unaware of fixed point representation.
My RB can can be used without any change.
Br,
Anshuman.
>
> Thanks.
> --
> Ashutosh
WARNING: multiple messages have this Message-ID (diff)
From: "Gupta, Anshuman" <anshuman.gupta@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: linux-hwmon@vger.kernel.org, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, jon.ewins@intel.com,
Badal Nilawar <badal.nilawar@intel.com>,
riana.tauro@intel.com
Subject: Re: [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power
Date: Thu, 22 Sep 2022 10:54:12 +0530 [thread overview]
Message-ID: <5c88044c-7ad6-80aa-634b-139532f9bf59@intel.com> (raw)
In-Reply-To: <87fsgkm71w.wl-ashutosh.dixit@intel.com>
On 9/22/2022 8:47 AM, Dixit, Ashutosh wrote:
> On Wed, 21 Sep 2022 08:07:15 -0700, Gupta, Anshuman wrote:
>>
>
> Hi Anshuman,
>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 55c35903adca..956e5298ef1e 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6644,6 +6644,12 @@
>>> #define DG1_PCODE_STATUS 0x7E
>>> #define DG1_UNCORE_GET_INIT_STATUS 0x0
>>> #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
>>> +#define PCODE_POWER_SETUP 0x7C
>>> +#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
>>> +#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
>>> +#define POWER_SETUP_I1_WATTS REG_BIT(31)
>>> +#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
>> Could please add some comment to explain, why POWER_SETUP_I1_SHIFT = 6,
>> what is excatly 10.6 fixed point format ?
>> With that.
>> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> 10.6 fixed point format means a 16 bit number is represented as x.y where x
> are the top 10 bits and y are the bottom 6 bits. The float value of this 16
> bit number is (x + (y / 2^6)), so (x + (y / 64)). For example the number
> 0x8008 will have the value (1 * 2^9 + 8 / 2^6) == 512.125. Note that the
> hexadecimal number 0x8008 == 32776 and 512.125 == 32776 / 64 which is why
> POWER_SETUP_I1_SHIFT is 6 (2^6 == 64).
>
> Similarly, the 8.8 fixed point format is explained in
> gt/intel_gt_sysfs_pm.c. Do you think this needs a comment? I thought "10.6
> fixed point format" is a sufficient hint (fixed point numbers are fairly
> well known).
>
> An even trickier data format is in the patch "drm/i915/hwmon: Expose
> power1_max_interval" in hwm_power1_max_interval_show() but I think I have a
> long comment there.
Thanks for explaining this, i was unaware of fixed point representation.
My RB can can be used without any change.
Br,
Anshuman.
>
> Thanks.
> --
> Ashutosh
next prev parent reply other threads:[~2022-09-22 5:24 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-16 15:00 [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-16 15:00 ` [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-21 10:59 ` Gupta, Anshuman
2022-09-21 10:59 ` [Intel-gfx] " Gupta, Anshuman
2022-09-21 10:59 ` Gupta, Anshuman
2022-09-21 12:44 ` [Intel-gfx] " Andi Shyti
2022-09-21 12:44 ` Andi Shyti
2022-09-21 15:17 ` Nilawar, Badal
2022-09-21 15:17 ` Nilawar, Badal
2022-09-21 15:45 ` Andi Shyti
2022-09-21 15:45 ` Andi Shyti
2022-09-21 15:45 ` Andi Shyti
2022-09-24 3:10 ` Dixit, Ashutosh
2022-09-24 3:10 ` Dixit, Ashutosh
2022-09-24 3:10 ` Dixit, Ashutosh
2022-09-16 15:00 ` [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-21 11:08 ` Gupta, Anshuman
2022-09-21 11:08 ` [Intel-gfx] " Gupta, Anshuman
2022-09-21 11:08 ` Gupta, Anshuman
2022-09-16 15:00 ` [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-16 18:29 ` [Intel-gfx] " kernel test robot
2022-09-21 0:02 ` Dixit, Ashutosh
2022-09-21 0:02 ` [Intel-gfx] " Dixit, Ashutosh
2022-09-21 0:02 ` Dixit, Ashutosh
2022-09-21 11:44 ` [Intel-gfx] " Tvrtko Ursulin
2022-09-21 11:45 ` Gupta, Anshuman
2022-09-21 11:45 ` Gupta, Anshuman
2022-09-21 11:45 ` [Intel-gfx] " Gupta, Anshuman
2022-09-21 14:53 ` Nilawar, Badal
2022-09-21 14:53 ` [Intel-gfx] " Nilawar, Badal
2022-09-21 14:53 ` Nilawar, Badal
2022-09-22 7:08 ` Gupta, Anshuman
2022-09-22 7:08 ` [Intel-gfx] " Gupta, Anshuman
2022-09-22 7:08 ` Gupta, Anshuman
2022-09-23 2:26 ` Dixit, Ashutosh
2022-09-23 2:26 ` [Intel-gfx] " Dixit, Ashutosh
2022-09-23 2:26 ` Dixit, Ashutosh
2022-09-16 15:00 ` [PATCH 4/7] drm/i915/hwmon: Show device level energy usage Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-21 12:02 ` Gupta, Anshuman
2022-09-21 12:02 ` [Intel-gfx] " Gupta, Anshuman
2022-09-21 12:02 ` Gupta, Anshuman
2022-10-13 15:53 ` Dixit, Ashutosh
2022-10-13 15:53 ` [Intel-gfx] " Dixit, Ashutosh
2022-10-13 15:53 ` Dixit, Ashutosh
2022-09-16 15:00 ` [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-21 15:07 ` Gupta, Anshuman
2022-09-21 15:07 ` [Intel-gfx] " Gupta, Anshuman
2022-09-21 15:07 ` Gupta, Anshuman
2022-09-22 3:17 ` Dixit, Ashutosh
2022-09-22 3:17 ` Dixit, Ashutosh
2022-09-22 3:17 ` [Intel-gfx] " Dixit, Ashutosh
2022-09-22 5:24 ` Gupta, Anshuman [this message]
2022-09-22 5:24 ` Gupta, Anshuman
2022-09-22 5:24 ` Gupta, Anshuman
2022-09-16 15:00 ` [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-22 7:13 ` Gupta, Anshuman
2022-09-22 7:13 ` Gupta, Anshuman
2022-09-22 7:13 ` [Intel-gfx] " Gupta, Anshuman
2022-09-23 2:51 ` Dixit, Ashutosh
2022-09-23 2:51 ` [Intel-gfx] " Dixit, Ashutosh
2022-09-23 2:51 ` Dixit, Ashutosh
2022-09-23 4:23 ` Dixit, Ashutosh
2022-09-23 4:23 ` [Intel-gfx] " Dixit, Ashutosh
2022-09-23 4:23 ` Dixit, Ashutosh
2022-09-16 15:00 ` [PATCH 7/7] drm/i915/hwmon: Extend power/energy for XEHPSDV Badal Nilawar
2022-09-16 15:00 ` [Intel-gfx] " Badal Nilawar
2022-09-16 15:00 ` Badal Nilawar
2022-09-22 7:37 ` Gupta, Anshuman
2022-09-22 7:37 ` [Intel-gfx] " Gupta, Anshuman
2022-09-22 7:37 ` Gupta, Anshuman
2022-09-16 17:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add HWMON support (rev6) Patchwork
2022-09-16 17:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-16 17:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-09-19 10:45 ` Nilawar, Badal
2022-09-19 10:15 ` [PATCH 0/7] drm/i915: Add HWMON support Gupta, Anshuman
2022-09-19 10:15 ` [Intel-gfx] " Gupta, Anshuman
2022-09-19 10:15 ` Gupta, Anshuman
2022-09-19 12:13 ` Nilawar, Badal
2022-09-19 12:13 ` [Intel-gfx] " Nilawar, Badal
2022-09-19 12:13 ` Nilawar, Badal
2022-09-19 15:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add HWMON support (rev6) Patchwork
2022-09-19 17:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-10-13 15:45 [PATCH 0/7] drm/i915: Add HWMON support Ashutosh Dixit
2022-10-13 15:45 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Ashutosh Dixit
2022-09-27 5:50 [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-09-27 5:50 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-10-03 21:18 ` Andi Shyti
2022-10-03 21:18 ` Andi Shyti
2022-09-26 17:52 [PATCH 0/7] Add HWMON support Badal Nilawar
2022-09-26 17:52 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-09-23 19:56 [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-09-23 19:56 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-08-25 13:21 [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-08-25 13:21 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-08-18 19:38 [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-08-18 19:38 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-08-12 17:37 [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-08-12 17:37 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
2022-08-12 18:09 ` Guenter Roeck
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