From: Ben Dooks <ben.dooks@codethink.co.uk> To: Chen Lifu <chenlifu@huawei.com>, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, akira.tsukamoto@gmail.com, jszhang@kernel.org, wangkefeng.wang@huawei.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, alankao@andestech.com Subject: Re: [PATCH -next] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit Date: Mon, 18 Jul 2022 16:10:22 +0100 [thread overview] Message-ID: <5dcbc6e6-a5f4-a28e-b78a-9eddce1b7ca8@codethink.co.uk> (raw) In-Reply-To: <20220615014714.1650349-1-chenlifu@huawei.com> On 15/06/2022 02:47, Chen Lifu wrote: > Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly") > and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"), > if __clear_user and __copy_user return from an fixup branch, > CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that > S-mode memory accesses to pages that are accessible by U-mode will success. > Disable S-mode access to U-mode memory should clear SR_SUM bit. > > Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly") > Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code") > > Signed-off-by: Chen Lifu <chenlifu@huawei.com> I've not run tested this, but it does look correct Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk> > --- > arch/riscv/lib/uaccess.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S > index 8c475f4da308..ec486e5369d9 100644 > --- a/arch/riscv/lib/uaccess.S > +++ b/arch/riscv/lib/uaccess.S > @@ -173,11 +173,11 @@ ENTRY(__asm_copy_from_user) > ret > > /* Exception fixup code */ > 10: > /* Disable access to user memory */ > - csrs CSR_STATUS, t6 > + csrc CSR_STATUS, t6 > mv a0, t5 > ret > ENDPROC(__asm_copy_to_user) > ENDPROC(__asm_copy_from_user) > EXPORT_SYMBOL(__asm_copy_to_user) > @@ -225,10 +225,10 @@ ENTRY(__clear_user) > j 3b > > /* Exception fixup code */ > 11: > /* Disable access to user memory */ > - csrs CSR_STATUS, t6 > + csrc CSR_STATUS, t6 > mv a0, a1 > ret > ENDPROC(__clear_user) > EXPORT_SYMBOL(__clear_user) -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Ben Dooks <ben.dooks@codethink.co.uk> To: Chen Lifu <chenlifu@huawei.com>, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, akira.tsukamoto@gmail.com, jszhang@kernel.org, wangkefeng.wang@huawei.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, alankao@andestech.com Subject: Re: [PATCH -next] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit Date: Mon, 18 Jul 2022 16:10:22 +0100 [thread overview] Message-ID: <5dcbc6e6-a5f4-a28e-b78a-9eddce1b7ca8@codethink.co.uk> (raw) In-Reply-To: <20220615014714.1650349-1-chenlifu@huawei.com> On 15/06/2022 02:47, Chen Lifu wrote: > Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly") > and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"), > if __clear_user and __copy_user return from an fixup branch, > CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that > S-mode memory accesses to pages that are accessible by U-mode will success. > Disable S-mode access to U-mode memory should clear SR_SUM bit. > > Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly") > Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code") > > Signed-off-by: Chen Lifu <chenlifu@huawei.com> I've not run tested this, but it does look correct Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk> > --- > arch/riscv/lib/uaccess.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S > index 8c475f4da308..ec486e5369d9 100644 > --- a/arch/riscv/lib/uaccess.S > +++ b/arch/riscv/lib/uaccess.S > @@ -173,11 +173,11 @@ ENTRY(__asm_copy_from_user) > ret > > /* Exception fixup code */ > 10: > /* Disable access to user memory */ > - csrs CSR_STATUS, t6 > + csrc CSR_STATUS, t6 > mv a0, t5 > ret > ENDPROC(__asm_copy_to_user) > ENDPROC(__asm_copy_from_user) > EXPORT_SYMBOL(__asm_copy_to_user) > @@ -225,10 +225,10 @@ ENTRY(__clear_user) > j 3b > > /* Exception fixup code */ > 11: > /* Disable access to user memory */ > - csrs CSR_STATUS, t6 > + csrc CSR_STATUS, t6 > mv a0, a1 > ret > ENDPROC(__clear_user) > EXPORT_SYMBOL(__clear_user) -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
next prev parent reply other threads:[~2022-07-18 15:11 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-15 1:47 [PATCH -next] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit Chen Lifu 2022-06-15 1:47 ` Chen Lifu 2022-06-28 12:58 ` chenlifu 2022-06-28 12:58 ` chenlifu 2022-07-15 3:47 ` chenlifu 2022-07-15 3:47 ` chenlifu 2022-08-09 11:01 ` chenlifu 2022-08-09 11:01 ` chenlifu 2022-07-18 15:10 ` Ben Dooks [this message] 2022-07-18 15:10 ` Ben Dooks 2022-08-10 22:01 ` Palmer Dabbelt 2022-08-10 22:01 ` Palmer Dabbelt
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