From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, mhiramat@kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v5 1/9] riscv: add macro to get instruction length
Date: Wed, 8 Apr 2020 15:56:56 +0800 [thread overview]
Message-ID: <621303b9cdea215af57329b401b15750c1f683ab.1586332296.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1586332296.git.zong.li@sifive.com>
Extract the calculation of instruction length for common use.
Signed-off-by: Zong Li <zong.li@sifive.com>
---
arch/riscv/include/asm/bug.h | 8 ++++++++
arch/riscv/kernel/traps.c | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/bug.h b/arch/riscv/include/asm/bug.h
index 75604fec1b1b..d6f1ec08d97b 100644
--- a/arch/riscv/include/asm/bug.h
+++ b/arch/riscv/include/asm/bug.h
@@ -19,6 +19,14 @@
#define __BUG_INSN_32 _UL(0x00100073) /* ebreak */
#define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */
+#define GET_INSN_LENGTH(insn) \
+({ \
+ unsigned long __len; \
+ __len = ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? \
+ 4UL : 2UL; \
+ __len; \
+})
+
typedef u32 bug_insn_t;
#ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index ffb3d94bf0cc..a4d136355f78 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -118,7 +118,8 @@ static inline unsigned long get_break_insn_length(unsigned long pc)
if (probe_kernel_address((bug_insn_t *)pc, insn))
return 0;
- return (((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? 4UL : 2UL);
+
+ return GET_INSN_LENGTH(insn);
}
asmlinkage __visible void do_trap_break(struct pt_regs *regs)
--
2.26.0
next prev parent reply other threads:[~2020-04-08 7:57 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 7:56 [PATCH v5 0/9] Support strict kernel memory permissions for security Zong Li
2020-04-08 7:56 ` Zong Li [this message]
2020-04-18 0:22 ` [PATCH v5 1/9] riscv: add macro to get instruction length Palmer Dabbelt
2020-04-18 0:22 ` Palmer Dabbelt
2020-04-08 7:56 ` [PATCH v5 2/9] riscv: introduce interfaces to patch kernel code Zong Li
2020-04-09 1:12 ` Masami Hiramatsu
2020-04-09 1:12 ` Masami Hiramatsu
2020-04-18 0:22 ` Palmer Dabbelt
2020-04-18 0:22 ` Palmer Dabbelt
2020-04-08 7:56 ` [PATCH v5 3/9] riscv: patch code by fixmap mapping Zong Li
2020-04-18 0:22 ` Palmer Dabbelt
2020-04-18 0:22 ` Palmer Dabbelt
2020-04-08 7:56 ` [PATCH v5 4/9] riscv: add ARCH_HAS_SET_MEMORY support Zong Li
2020-04-08 7:56 ` Zong Li
2020-04-08 7:57 ` [PATCH v5 5/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Zong Li
2020-04-08 7:57 ` Zong Li
2020-04-08 7:57 ` [PATCH v5 6/9] riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Zong Li
2020-04-08 7:57 ` Zong Li
2020-04-08 7:57 ` [PATCH v5 7/9] riscv: move exception table immediately after RO_DATA Zong Li
2020-04-08 7:57 ` Zong Li
2020-04-08 7:57 ` [PATCH v5 8/9] riscv: add alignment for text, rodata and data sections Zong Li
2020-04-08 7:57 ` Zong Li
2020-04-08 7:57 ` [PATCH v5 9/9] riscv: add STRICT_KERNEL_RWX support Zong Li
2020-04-18 0:30 ` Palmer Dabbelt
2020-04-18 0:30 ` Palmer Dabbelt
2020-04-19 23:50 ` Damien Le Moal
2020-04-19 23:50 ` Damien Le Moal
2020-04-20 18:27 ` [PATCH v5 0/9] Support strict kernel memory permissions for security Palmer Dabbelt
2020-04-20 18:27 ` Palmer Dabbelt
2020-04-21 5:36 ` Zong Li
2020-04-21 5:36 ` Zong Li
2020-04-21 6:20 ` Anup Patel
2020-04-21 6:20 ` Anup Patel
2020-04-21 6:29 ` Zong Li
2020-04-21 6:29 ` Zong Li
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