From: Zong Li <zong.li@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, mhiramat@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li <zong.li@sifive.com>, Palmer Dabbelt <palmerdabbelt@google.com> Subject: [PATCH v5 8/9] riscv: add alignment for text, rodata and data sections Date: Wed, 8 Apr 2020 15:57:03 +0800 [thread overview] Message-ID: <d78c601d553dde791057b54252064221f960546e.1586332296.git.zong.li@sifive.com> (raw) In-Reply-To: <cover.1586332296.git.zong.li@sifive.com> The kernel mapping will tried to optimize its mapping by using bigger size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in rv32. To ensure that the start address of these sections could fit the mapping entry size, make them align to the biggest alignment. Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc., are invisible in linker script. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> --- arch/riscv/include/asm/set_memory.h | 13 +++++++++++++ arch/riscv/kernel/vmlinux.lds.S | 5 ++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h index 620d81c372d9..4c5bae7ca01c 100644 --- a/arch/riscv/include/asm/set_memory.h +++ b/arch/riscv/include/asm/set_memory.h @@ -6,6 +6,7 @@ #ifndef _ASM_RISCV_SET_MEMORY_H #define _ASM_RISCV_SET_MEMORY_H +#ifndef __ASSEMBLY__ /* * Functions to change memory attributes. */ @@ -24,4 +25,16 @@ static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } int set_direct_map_invalid_noflush(struct page *page); int set_direct_map_default_noflush(struct page *page); +#endif /* __ASSEMBLY__ */ + +#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX +#ifdef CONFIG_64BIT +#define SECTION_ALIGN (1 << 21) +#else +#define SECTION_ALIGN (1 << 22) +#endif +#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */ +#define SECTION_ALIGN L1_CACHE_BYTES +#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */ + #endif /* _ASM_RISCV_SET_MEMORY_H */ diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S index 02e948b620af..ef87deea0350 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -9,6 +9,7 @@ #include <asm/page.h> #include <asm/cache.h> #include <asm/thread_info.h> +#include <asm/set_memory.h> OUTPUT_ARCH(riscv) ENTRY(_start) @@ -36,6 +37,7 @@ SECTIONS PERCPU_SECTION(L1_CACHE_BYTES) __init_end = .; + . = ALIGN(SECTION_ALIGN); .text : { _text = .; _stext = .; @@ -53,13 +55,14 @@ SECTIONS /* Start of data section */ _sdata = .; - RO_DATA(L1_CACHE_BYTES) + RO_DATA(SECTION_ALIGN) .srodata : { *(.srodata*) } EXCEPTION_TABLE(0x10) + . = ALIGN(SECTION_ALIGN); _data = .; RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) -- 2.26.0
WARNING: multiple messages have this Message-ID (diff)
From: Zong Li <zong.li@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, mhiramat@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Palmer Dabbelt <palmerdabbelt@google.com>, Zong Li <zong.li@sifive.com> Subject: [PATCH v5 8/9] riscv: add alignment for text, rodata and data sections Date: Wed, 8 Apr 2020 15:57:03 +0800 [thread overview] Message-ID: <d78c601d553dde791057b54252064221f960546e.1586332296.git.zong.li@sifive.com> (raw) In-Reply-To: <cover.1586332296.git.zong.li@sifive.com> The kernel mapping will tried to optimize its mapping by using bigger size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in rv32. To ensure that the start address of these sections could fit the mapping entry size, make them align to the biggest alignment. Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc., are invisible in linker script. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> --- arch/riscv/include/asm/set_memory.h | 13 +++++++++++++ arch/riscv/kernel/vmlinux.lds.S | 5 ++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h index 620d81c372d9..4c5bae7ca01c 100644 --- a/arch/riscv/include/asm/set_memory.h +++ b/arch/riscv/include/asm/set_memory.h @@ -6,6 +6,7 @@ #ifndef _ASM_RISCV_SET_MEMORY_H #define _ASM_RISCV_SET_MEMORY_H +#ifndef __ASSEMBLY__ /* * Functions to change memory attributes. */ @@ -24,4 +25,16 @@ static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } int set_direct_map_invalid_noflush(struct page *page); int set_direct_map_default_noflush(struct page *page); +#endif /* __ASSEMBLY__ */ + +#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX +#ifdef CONFIG_64BIT +#define SECTION_ALIGN (1 << 21) +#else +#define SECTION_ALIGN (1 << 22) +#endif +#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */ +#define SECTION_ALIGN L1_CACHE_BYTES +#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */ + #endif /* _ASM_RISCV_SET_MEMORY_H */ diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S index 02e948b620af..ef87deea0350 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -9,6 +9,7 @@ #include <asm/page.h> #include <asm/cache.h> #include <asm/thread_info.h> +#include <asm/set_memory.h> OUTPUT_ARCH(riscv) ENTRY(_start) @@ -36,6 +37,7 @@ SECTIONS PERCPU_SECTION(L1_CACHE_BYTES) __init_end = .; + . = ALIGN(SECTION_ALIGN); .text : { _text = .; _stext = .; @@ -53,13 +55,14 @@ SECTIONS /* Start of data section */ _sdata = .; - RO_DATA(L1_CACHE_BYTES) + RO_DATA(SECTION_ALIGN) .srodata : { *(.srodata*) } EXCEPTION_TABLE(0x10) + . = ALIGN(SECTION_ALIGN); _data = .; RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) -- 2.26.0
next prev parent reply other threads:[~2020-04-08 7:57 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-08 7:56 [PATCH v5 0/9] Support strict kernel memory permissions for security Zong Li 2020-04-08 7:56 ` [PATCH v5 1/9] riscv: add macro to get instruction length Zong Li 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-08 7:56 ` [PATCH v5 2/9] riscv: introduce interfaces to patch kernel code Zong Li 2020-04-09 1:12 ` Masami Hiramatsu 2020-04-09 1:12 ` Masami Hiramatsu 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-08 7:56 ` [PATCH v5 3/9] riscv: patch code by fixmap mapping Zong Li 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-08 7:56 ` [PATCH v5 4/9] riscv: add ARCH_HAS_SET_MEMORY support Zong Li 2020-04-08 7:56 ` Zong Li 2020-04-08 7:57 ` [PATCH v5 5/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Zong Li 2020-04-08 7:57 ` Zong Li 2020-04-08 7:57 ` [PATCH v5 6/9] riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Zong Li 2020-04-08 7:57 ` Zong Li 2020-04-08 7:57 ` [PATCH v5 7/9] riscv: move exception table immediately after RO_DATA Zong Li 2020-04-08 7:57 ` Zong Li 2020-04-08 7:57 ` Zong Li [this message] 2020-04-08 7:57 ` [PATCH v5 8/9] riscv: add alignment for text, rodata and data sections Zong Li 2020-04-08 7:57 ` [PATCH v5 9/9] riscv: add STRICT_KERNEL_RWX support Zong Li 2020-04-18 0:30 ` Palmer Dabbelt 2020-04-18 0:30 ` Palmer Dabbelt 2020-04-19 23:50 ` Damien Le Moal 2020-04-19 23:50 ` Damien Le Moal 2020-04-20 18:27 ` [PATCH v5 0/9] Support strict kernel memory permissions for security Palmer Dabbelt 2020-04-20 18:27 ` Palmer Dabbelt 2020-04-21 5:36 ` Zong Li 2020-04-21 5:36 ` Zong Li 2020-04-21 6:20 ` Anup Patel 2020-04-21 6:20 ` Anup Patel 2020-04-21 6:29 ` Zong Li 2020-04-21 6:29 ` Zong Li
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