From: Joao Pinto <Joao.Pinto@synopsys.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Arnd Bergmann <arnd@arndb.de>
Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org,
nsekhar@ti.com
Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Fri, 13 Jan 2017 16:34:26 +0000 [thread overview]
Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> (raw)
In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com>
Hi Kishon,
Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Some platforms (like dra7xx) require only the least 28 bits of the
> corresponding 32 bit CPU address to be programmed in the address
> translation unit. This modified address is stored in io_base/mem_base/
> cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
> host mode where the address range is fixed, device mode requires
> different addresses to be programmed based on the host buffer address.
> Add a new ops to get the least 28 bits of the corresponding 32 bit
> CPU address and invoke it before programming the address translation
> unit.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 3 +++
> drivers/pci/dwc/pcie-designware.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index bed1999..d68bc7b 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
> {
> u32 retries, val;
>
> + if (pp->ops->cpu_addr_fixup)
> + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
> +
> if (pp->iatu_unroll_enabled) {
> dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
> lower_32_bits(cpu_addr));
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index a567ea2..32f4602 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -54,6 +54,7 @@ struct pcie_port {
> };
>
> struct pcie_host_ops {
> + u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
> void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
> int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
>
I think this is an acceptable fixup, I am ok with it.
Reviewed-By: Joao Pinto <jpinto@synopsys.com>
Joao
WARNING: multiple messages have this Message-ID (diff)
From: Joao Pinto <Joao.Pinto@synopsys.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Arnd Bergmann <arnd@arndb.de>
Cc: <linux-pci@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-samsung-soc@vger.kernel.org>,
<linuxppc-dev@lists.ozlabs.org>, <linux-arm-kernel@axis.com>,
<linux-arm-msm@vger.kernel.org>, <nsekhar@ti.com>
Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Fri, 13 Jan 2017 16:34:26 +0000 [thread overview]
Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> (raw)
In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com>
Hi Kishon,
Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Some platforms (like dra7xx) require only the least 28 bits of the
> corresponding 32 bit CPU address to be programmed in the address
> translation unit. This modified address is stored in io_base/mem_base/
> cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
> host mode where the address range is fixed, device mode requires
> different addresses to be programmed based on the host buffer address.
> Add a new ops to get the least 28 bits of the corresponding 32 bit
> CPU address and invoke it before programming the address translation
> unit.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 3 +++
> drivers/pci/dwc/pcie-designware.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index bed1999..d68bc7b 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
> {
> u32 retries, val;
>
> + if (pp->ops->cpu_addr_fixup)
> + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
> +
> if (pp->iatu_unroll_enabled) {
> dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
> lower_32_bits(cpu_addr));
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index a567ea2..32f4602 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -54,6 +54,7 @@ struct pcie_port {
> };
>
> struct pcie_host_ops {
> + u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
> void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
> int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
>
I think this is an acceptable fixup, I am ok with it.
Reviewed-By: Joao Pinto <jpinto@synopsys.com>
Joao
WARNING: multiple messages have this Message-ID (diff)
From: Joao Pinto <Joao.Pinto@synopsys.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-doc@vger.kernel.org, linux-pci@vger.kernel.org,
nsekhar@ti.com, linux-kernel@vger.kernel.org,
linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org,
linux-omap@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Fri, 13 Jan 2017 16:34:26 +0000 [thread overview]
Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> (raw)
In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com>
Hi Kishon,
=C0s 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Some platforms (like dra7xx) require only the least 28 bits of the
> corresponding 32 bit CPU address to be programmed in the address
> translation unit. This modified address is stored in io_base/mem_base/
> cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
> host mode where the address range is fixed, device mode requires
> different addresses to be programmed based on the host buffer address.
> Add a new ops to get the least 28 bits of the corresponding 32 bit
> CPU address and invoke it before programming the address translation
> unit.
> =
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 3 +++
> drivers/pci/dwc/pcie-designware.h | 1 +
> 2 files changed, 4 insertions(+)
> =
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-des=
ignware.c
> index bed1999..d68bc7b 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_por=
t *pp, int index,
> {
> u32 retries, val;
> =
> + if (pp->ops->cpu_addr_fixup)
> + cpu_addr =3D pp->ops->cpu_addr_fixup(cpu_addr);
> +
> if (pp->iatu_unroll_enabled) {
> dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
> lower_32_bits(cpu_addr));
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-des=
ignware.h
> index a567ea2..32f4602 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -54,6 +54,7 @@ struct pcie_port {
> };
> =
> struct pcie_host_ops {
> + u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
> void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
> int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
> =
I think this is an acceptable fixup, I am ok with it.
Reviewed-By: Joao Pinto <jpinto@synopsys.com>
Joao
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Joao.Pinto@synopsys.com (Joao Pinto)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Fri, 13 Jan 2017 16:34:26 +0000 [thread overview]
Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com> (raw)
In-Reply-To: <1484216786-17292-3-git-send-email-kishon@ti.com>
Hi Kishon,
?s 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Some platforms (like dra7xx) require only the least 28 bits of the
> corresponding 32 bit CPU address to be programmed in the address
> translation unit. This modified address is stored in io_base/mem_base/
> cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
> host mode where the address range is fixed, device mode requires
> different addresses to be programmed based on the host buffer address.
> Add a new ops to get the least 28 bits of the corresponding 32 bit
> CPU address and invoke it before programming the address translation
> unit.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 3 +++
> drivers/pci/dwc/pcie-designware.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index bed1999..d68bc7b 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
> {
> u32 retries, val;
>
> + if (pp->ops->cpu_addr_fixup)
> + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
> +
> if (pp->iatu_unroll_enabled) {
> dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
> lower_32_bits(cpu_addr));
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index a567ea2..32f4602 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -54,6 +54,7 @@ struct pcie_port {
> };
>
> struct pcie_host_ops {
> + u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
> void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
> int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
>
I think this is an acceptable fixup, I am ok with it.
Reviewed-By: Joao Pinto <jpinto@synopsys.com>
Joao
next prev parent reply other threads:[~2017-01-13 16:34 UTC|newest]
Thread overview: 252+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 10:25 [PATCH 00/37] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 16:34 ` Joao Pinto [this message]
2017-01-13 16:34 ` Joao Pinto
2017-01-13 16:34 ` Joao Pinto
2017-01-13 16:34 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 03/37] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 04/37] PCI: dwc: designware: Move the register defines to designware header file Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 16:35 ` Joao Pinto
2017-01-13 16:35 ` Joao Pinto
2017-01-13 16:35 ` Joao Pinto
2017-01-13 16:35 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 05/37] PCI: dwc: Add platform_set_drvdata Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 17:16 ` Joao Pinto
2017-01-13 17:16 ` Joao Pinto
2017-01-13 17:16 ` Joao Pinto
2017-01-13 17:16 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 06/37] PCI: dwc: Rename cfg_read/cfg_write to read/write Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 16:36 ` Joao Pinto
2017-01-13 16:36 ` Joao Pinto
2017-01-13 16:36 ` Joao Pinto
2017-01-13 16:36 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 17:22 ` Joao Pinto
2017-01-13 17:22 ` Joao Pinto
2017-01-13 17:22 ` Joao Pinto
2017-01-13 17:22 ` Joao Pinto
2017-01-12 10:25 ` [RFT PATCH 08/37] PCI: dwc: Split *struct pcie_port* into host only and core structures Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 17:13 ` Joao Pinto
2017-01-13 17:13 ` Joao Pinto
2017-01-13 17:13 ` Joao Pinto
2017-01-13 17:13 ` Joao Pinto
2017-01-16 5:19 ` Kishon Vijay Abraham I
2017-01-16 5:19 ` Kishon Vijay Abraham I
2017-01-16 5:19 ` Kishon Vijay Abraham I
2017-01-16 5:19 ` Kishon Vijay Abraham I
[not found] ` <587C57FD.7050601-l0cyMroinI0@public.gmane.org>
2017-01-16 10:23 ` Joao Pinto
2017-01-16 10:23 ` Joao Pinto
2017-01-16 10:23 ` Joao Pinto
2017-01-16 10:23 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 10/37] PCI: dwc: designware: Fix style errors in pcie-designware.c Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-13 16:38 ` Joao Pinto
2017-01-13 16:38 ` Joao Pinto
2017-01-13 16:38 ` Joao Pinto
2017-01-13 16:38 ` Joao Pinto
2017-01-12 10:26 ` [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-13 16:49 ` Joao Pinto
2017-01-13 16:49 ` Joao Pinto
2017-01-13 16:49 ` Joao Pinto
2017-01-13 16:49 ` Joao Pinto
2017-01-16 5:21 ` Kishon Vijay Abraham I
2017-01-16 5:21 ` Kishon Vijay Abraham I
2017-01-16 5:21 ` Kishon Vijay Abraham I
2017-01-16 5:21 ` Kishon Vijay Abraham I
[not found] ` <587C586C.6070003-l0cyMroinI0@public.gmane.org>
2017-01-16 10:27 ` Joao Pinto
2017-01-16 10:27 ` Joao Pinto
2017-01-16 10:27 ` Joao Pinto
2017-01-16 10:27 ` Joao Pinto
2017-01-16 11:30 ` Kishon Vijay Abraham I
2017-01-16 11:30 ` Kishon Vijay Abraham I
2017-01-16 11:30 ` Kishon Vijay Abraham I
2017-01-16 11:30 ` Kishon Vijay Abraham I
[not found] ` <587CAEBD.1010803-l0cyMroinI0@public.gmane.org>
2017-01-16 13:38 ` Joao Pinto
2017-01-16 13:38 ` Joao Pinto
2017-01-16 13:38 ` Joao Pinto
2017-01-16 13:38 ` Joao Pinto
2017-01-12 10:26 ` [PATCH 12/37] PCI: dwc: Create a new config symbol to enable pci dwc host Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-13 17:50 ` Joao Pinto
2017-01-13 17:50 ` Joao Pinto
2017-01-13 17:50 ` Joao Pinto
2017-01-13 17:50 ` Joao Pinto
2017-01-16 5:22 ` Kishon Vijay Abraham I
2017-01-16 5:22 ` Kishon Vijay Abraham I
2017-01-16 5:22 ` Kishon Vijay Abraham I
2017-01-16 5:22 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 13/37] PCI: dwc: Remove dependency of designware to CONFIG_PCI Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 14/37] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 15/37] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 16/37] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-13 18:06 ` Christoph Hellwig
2017-01-13 18:06 ` Christoph Hellwig
2017-01-13 18:06 ` Christoph Hellwig
2017-01-13 18:06 ` Christoph Hellwig
2017-01-16 6:01 ` Kishon Vijay Abraham I
2017-01-16 6:01 ` Kishon Vijay Abraham I
2017-01-16 6:01 ` Kishon Vijay Abraham I
2017-01-16 6:01 ` Kishon Vijay Abraham I
2017-01-16 15:51 ` Christoph Hellwig
2017-01-16 15:51 ` Christoph Hellwig
2017-01-16 15:51 ` Christoph Hellwig
2017-01-16 15:51 ` Christoph Hellwig
2017-01-12 10:26 ` [PATCH 17/37] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 18/37] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 19/37] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 20/37] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 21/37] PCI: dwc: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 22/37] PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 23/37] PCI: dwc: Add *ops* to start and stop pcie link Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 24/37] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 25/37] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-18 21:36 ` Rob Herring
2017-01-18 21:36 ` Rob Herring
2017-01-18 21:36 ` Rob Herring
2017-01-18 21:36 ` Rob Herring
2017-01-12 10:26 ` [PATCH 26/37] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 27/37] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 28/37] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-18 21:45 ` Rob Herring
2017-01-18 21:45 ` Rob Herring
2017-01-18 21:45 ` Rob Herring
2017-01-12 10:26 ` [PATCH 29/37] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 30/37] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-18 21:46 ` Rob Herring
2017-01-18 21:46 ` Rob Herring
2017-01-18 21:46 ` Rob Herring
2017-01-18 21:46 ` Rob Herring
2017-02-16 8:33 ` Kishon Vijay Abraham I
2017-02-16 8:33 ` Kishon Vijay Abraham I
2017-02-16 8:33 ` Kishon Vijay Abraham I
2017-02-16 8:33 ` Kishon Vijay Abraham I
[not found] ` <1484216786-17292-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
2017-01-12 10:25 ` [PATCH 01/37] PCI: dwc: dra7xx: Group all host related setup in add_pcie_port Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 31/37] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-24 16:02 ` Christoph Hellwig
2017-01-24 16:02 ` Christoph Hellwig
[not found] ` <20170124160224.GA23528-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
2017-01-25 5:40 ` Kishon Vijay Abraham I
2017-01-25 5:40 ` Kishon Vijay Abraham I
2017-01-25 5:40 ` Kishon Vijay Abraham I
2017-01-25 5:40 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 32/37] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 33/37] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 34/37] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 35/37] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-13 17:15 ` Tony Lindgren
2017-01-13 17:15 ` Tony Lindgren
2017-01-13 17:15 ` Tony Lindgren
2017-01-16 6:05 ` Kishon Vijay Abraham I
2017-01-16 6:05 ` Kishon Vijay Abraham I
2017-01-16 6:05 ` Kishon Vijay Abraham I
2017-01-16 6:05 ` Kishon Vijay Abraham I
2017-01-20 18:28 ` Tony Lindgren
2017-01-20 18:28 ` Tony Lindgren
2017-01-20 18:28 ` Tony Lindgren
2017-01-12 10:26 ` [PATCH 37/37] ARM: dts: DRA7: Add pcie1 dt node for EP mode Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` Kishon Vijay Abraham I
2017-01-20 18:30 ` Tony Lindgren
2017-01-20 18:30 ` Tony Lindgren
2017-01-20 18:30 ` Tony Lindgren
[not found] ` <20170120183000.GF7403-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
2017-02-16 10:00 ` Kishon Vijay Abraham I
2017-02-16 10:00 ` Kishon Vijay Abraham I
2017-02-16 10:00 ` Kishon Vijay Abraham I
2017-02-16 10:00 ` Kishon Vijay Abraham I
2017-02-01 12:31 ` [PATCH 00/37] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-02-01 12:31 ` Kishon Vijay Abraham I
2017-02-14 23:55 ` Bjorn Helgaas
2017-02-14 23:55 ` Bjorn Helgaas
2017-02-15 13:30 ` Kishon Vijay Abraham I
2017-02-15 13:30 ` Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com \
--to=joao.pinto@synopsys.com \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=jingoohan1@gmail.com \
--cc=kishon@ti.com \
--cc=linux-arm-kernel@axis.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=nsekhar@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.