From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Samuel Holland <samuel.holland@sifive.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Eric Lin <eric.lin@sifive.com>, Conor Dooley <conor@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property
Date: Sun, 18 Feb 2024 19:35:35 +0100 [thread overview]
Message-ID: <6ac4005b-01e6-48c2-971e-d6a127134d13@linaro.org> (raw)
In-Reply-To: <72221da1-4a1a-4947-a202-9de203032f5c@sifive.com>
On 18/02/2024 16:29, Samuel Holland wrote:
> Hi Krzysztof,
>
> On 2024-02-17 3:00 AM, Krzysztof Kozlowski wrote:
>> On 16/02/2024 01:08, Samuel Holland wrote:
>>> The SiFive Composable Cache controller contains an optional PMU with a
>>> configurable number of event counters. Document a property which
>>
>> Configurable in what context? By chip designers or by OS? Why this
>> cannot be deduced from the compatible?
>
> This parameter is configurable by the chip designers.
>
> The information certainly can be deduced from the SoC-specific compatible
> string, but doing so makes the driver only work on that specific list of SoCs.
Usually that's exactly what's expected, so why here usual approach is wrong?
> When provided via a property, the driver can work without changes on any SoC
> that uses this IP block. (None of the SoCs currently listed in the binding
Sorry, properties are not a work-around for missing compatibles.
> contain a PMU, so there is no backward compatibility concern with adding the new
> property.)
>
> My understanding of the purpose of the SoC-specific compatible string is to
> handle eventualities (silicon bugs, integration quirks, etc.), not to
> intentionally limit the driver to a narrow list of hardware.
Depends what is the hardware. For most of licensed blocks, the final
design is the hardware so equals to its compatible.
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Samuel Holland <samuel.holland@sifive.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Eric Lin <eric.lin@sifive.com>, Conor Dooley <conor@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property
Date: Sun, 18 Feb 2024 19:35:35 +0100 [thread overview]
Message-ID: <6ac4005b-01e6-48c2-971e-d6a127134d13@linaro.org> (raw)
In-Reply-To: <72221da1-4a1a-4947-a202-9de203032f5c@sifive.com>
On 18/02/2024 16:29, Samuel Holland wrote:
> Hi Krzysztof,
>
> On 2024-02-17 3:00 AM, Krzysztof Kozlowski wrote:
>> On 16/02/2024 01:08, Samuel Holland wrote:
>>> The SiFive Composable Cache controller contains an optional PMU with a
>>> configurable number of event counters. Document a property which
>>
>> Configurable in what context? By chip designers or by OS? Why this
>> cannot be deduced from the compatible?
>
> This parameter is configurable by the chip designers.
>
> The information certainly can be deduced from the SoC-specific compatible
> string, but doing so makes the driver only work on that specific list of SoCs.
Usually that's exactly what's expected, so why here usual approach is wrong?
> When provided via a property, the driver can work without changes on any SoC
> that uses this IP block. (None of the SoCs currently listed in the binding
Sorry, properties are not a work-around for missing compatibles.
> contain a PMU, so there is no backward compatibility concern with adding the new
> property.)
>
> My understanding of the purpose of the SoC-specific compatible string is to
> handle eventualities (silicon bugs, integration quirks, etc.), not to
> intentionally limit the driver to a narrow list of hardware.
Depends what is the hardware. For most of licensed blocks, the final
design is the hardware so equals to its compatible.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Samuel Holland <samuel.holland@sifive.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Eric Lin <eric.lin@sifive.com>, Conor Dooley <conor@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property
Date: Sun, 18 Feb 2024 19:35:35 +0100 [thread overview]
Message-ID: <6ac4005b-01e6-48c2-971e-d6a127134d13@linaro.org> (raw)
In-Reply-To: <72221da1-4a1a-4947-a202-9de203032f5c@sifive.com>
On 18/02/2024 16:29, Samuel Holland wrote:
> Hi Krzysztof,
>
> On 2024-02-17 3:00 AM, Krzysztof Kozlowski wrote:
>> On 16/02/2024 01:08, Samuel Holland wrote:
>>> The SiFive Composable Cache controller contains an optional PMU with a
>>> configurable number of event counters. Document a property which
>>
>> Configurable in what context? By chip designers or by OS? Why this
>> cannot be deduced from the compatible?
>
> This parameter is configurable by the chip designers.
>
> The information certainly can be deduced from the SoC-specific compatible
> string, but doing so makes the driver only work on that specific list of SoCs.
Usually that's exactly what's expected, so why here usual approach is wrong?
> When provided via a property, the driver can work without changes on any SoC
> that uses this IP block. (None of the SoCs currently listed in the binding
Sorry, properties are not a work-around for missing compatibles.
> contain a PMU, so there is no backward compatibility concern with adding the new
> property.)
>
> My understanding of the purpose of the SoC-specific compatible string is to
> handle eventualities (silicon bugs, integration quirks, etc.), not to
> intentionally limit the driver to a narrow list of hardware.
Depends what is the hardware. For most of licensed blocks, the final
design is the hardware so equals to its compatible.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-02-18 18:35 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 0:08 [PATCH v1 0/6] SiFive cache controller PMU drivers Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-17 9:00 ` Krzysztof Kozlowski
2024-02-17 9:00 ` Krzysztof Kozlowski
2024-02-17 9:00 ` Krzysztof Kozlowski
2024-02-18 15:29 ` Samuel Holland
2024-02-18 15:29 ` Samuel Holland
2024-02-18 15:29 ` Samuel Holland
2024-02-18 18:35 ` Krzysztof Kozlowski [this message]
2024-02-18 18:35 ` Krzysztof Kozlowski
2024-02-18 18:35 ` Krzysztof Kozlowski
2024-02-22 19:36 ` Rob Herring
2024-02-22 19:36 ` Rob Herring
2024-02-22 19:36 ` Rob Herring
2024-04-09 15:03 ` Conor Dooley
2024-04-09 15:03 ` Conor Dooley
2024-04-09 15:03 ` Conor Dooley
2024-02-16 0:08 ` [PATCH v1 2/6] drivers/perf: Add SiFive Composable Cache PMU driver Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-19 11:29 ` Jonathan Cameron
2024-02-19 11:29 ` Jonathan Cameron
2024-02-19 11:29 ` Jonathan Cameron
2024-04-11 11:05 ` Robin Murphy
2024-04-11 11:05 ` Robin Murphy
2024-04-11 11:05 ` Robin Murphy
2024-02-16 0:08 ` [PATCH v1 3/6] dt-bindings: cache: Add SiFive Extensible Cache controller Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-17 9:09 ` Krzysztof Kozlowski
2024-02-17 9:09 ` Krzysztof Kozlowski
2024-02-17 9:09 ` Krzysztof Kozlowski
2024-02-18 15:50 ` Samuel Holland
2024-02-18 15:50 ` Samuel Holland
2024-02-18 15:50 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 4/6] drivers/perf: Add SiFive Extensible Cache PMU driver Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-19 11:40 ` Jonathan Cameron
2024-02-19 11:40 ` Jonathan Cameron
2024-02-19 11:40 ` Jonathan Cameron
2024-02-16 0:08 ` [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-17 9:12 ` Krzysztof Kozlowski
2024-02-17 9:12 ` Krzysztof Kozlowski
2024-02-17 9:12 ` Krzysztof Kozlowski
2024-02-18 15:33 ` Samuel Holland
2024-02-18 15:33 ` Samuel Holland
2024-02-18 15:33 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 6/6] drivers/perf: Add SiFive Private L2 Cache PMU driver Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 0:08 ` Samuel Holland
2024-02-16 10:05 ` [PATCH v1 0/6] SiFive cache controller PMU drivers Conor Dooley
2024-02-16 10:05 ` Conor Dooley
2024-02-16 10:05 ` Conor Dooley
2024-04-09 15:01 ` Conor Dooley
2024-04-09 15:01 ` Conor Dooley
2024-04-09 15:01 ` Conor Dooley
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