From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
mark.rutland@arm.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register
Date: Tue, 19 May 2020 14:44:28 +0100 [thread overview]
Message-ID: <6ad2dde0-455f-90a6-7b76-eda4fe8d6efe@arm.com> (raw)
In-Reply-To: <1589881254-10082-14-git-send-email-anshuman.khandual@arm.com>
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
> Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as
> per ARM DDI 0487F.a specification.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Will Deacon <will@kernel.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/include/asm/sysreg.h | 4 ++++
> arch/arm64/kernel/cpufeature.c | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 95fdfc5e9bd0..f9dd2c5ab074 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -734,6 +734,10 @@
> #endif
>
> /* id_aa64mmfr1 */
> +#define ID_AA64MMFR1_ETS_SHIFT 36
> +#define ID_AA64MMFR1_TWED_SHIFT 32
> +#define ID_AA64MMFR1_XNX_SHIFT 28
> +#define ID_AA64MMFR1_SPECSEI_SHIFT 24
> #define ID_AA64MMFR1_PAN_SHIFT 20
> #define ID_AA64MMFR1_LOR_SHIFT 16
> #define ID_AA64MMFR1_HPD_SHIFT 12
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 7ce19f97ba73..1f10ff7df705 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -299,6 +299,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
> };
>
> static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
SpecSEI must be HIGHER_SAFE, like we did for MMFR4 ?
Otherwise looks good to me.
Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org,
linux-kernel@vger.kernel.org, maz@kernel.org
Subject: Re: [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register
Date: Tue, 19 May 2020 14:44:28 +0100 [thread overview]
Message-ID: <6ad2dde0-455f-90a6-7b76-eda4fe8d6efe@arm.com> (raw)
In-Reply-To: <1589881254-10082-14-git-send-email-anshuman.khandual@arm.com>
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
> Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as
> per ARM DDI 0487F.a specification.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Will Deacon <will@kernel.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/include/asm/sysreg.h | 4 ++++
> arch/arm64/kernel/cpufeature.c | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 95fdfc5e9bd0..f9dd2c5ab074 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -734,6 +734,10 @@
> #endif
>
> /* id_aa64mmfr1 */
> +#define ID_AA64MMFR1_ETS_SHIFT 36
> +#define ID_AA64MMFR1_TWED_SHIFT 32
> +#define ID_AA64MMFR1_XNX_SHIFT 28
> +#define ID_AA64MMFR1_SPECSEI_SHIFT 24
> #define ID_AA64MMFR1_PAN_SHIFT 20
> #define ID_AA64MMFR1_LOR_SHIFT 16
> #define ID_AA64MMFR1_HPD_SHIFT 12
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 7ce19f97ba73..1f10ff7df705 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -299,6 +299,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
> };
>
> static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
SpecSEI must be HIGHER_SAFE, like we did for MMFR4 ?
Otherwise looks good to me.
Suzuki
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next prev parent reply other threads:[~2020-05-19 13:39 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 9:40 [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 01/17] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 02/17] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:44 ` Suzuki K Poulose
2020-05-19 10:44 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 04/17] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 05/17] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:46 ` Suzuki K Poulose
2020-05-19 10:46 ` Suzuki K Poulose
2020-05-19 10:46 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 06/17] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 07/17] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 08/17] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:53 ` Suzuki K Poulose
2020-05-19 10:53 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 09/17] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:56 ` Suzuki K Poulose
2020-05-19 10:56 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 10/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 11:11 ` Suzuki K Poulose
2020-05-19 11:11 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 11/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 11:13 ` Suzuki K Poulose
2020-05-19 11:13 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 12/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 13:32 ` Suzuki K Poulose
2020-05-19 13:32 ` Suzuki K Poulose
2020-05-24 23:08 ` Anshuman Khandual
2020-05-24 23:08 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 13:44 ` Suzuki K Poulose [this message]
2020-05-19 13:44 ` Suzuki K Poulose
2020-05-24 1:09 ` Anshuman Khandual
2020-05-24 1:09 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 14/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-20 13:56 ` Suzuki K Poulose
2020-05-20 13:56 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 15/17] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-20 13:57 ` Suzuki K Poulose
2020-05-20 13:57 ` Suzuki K Poulose
2020-05-24 1:08 ` Anshuman Khandual
2020-05-24 1:08 ` Anshuman Khandual
2020-05-25 10:46 ` Suzuki K Poulose
2020-05-25 10:46 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 16/17] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-20 13:58 ` Suzuki K Poulose
2020-05-20 13:58 ` Suzuki K Poulose
2020-05-21 15:19 ` [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Will Deacon
2020-05-21 15:19 ` Will Deacon
2020-05-21 15:19 ` Will Deacon
2020-05-25 12:39 ` Anshuman Khandual
2020-05-25 12:39 ` Anshuman Khandual
2020-05-25 12:39 ` Anshuman Khandual
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