RE: [PATCH] KVM: Qemu: Flush i-cache after ide-dma operation in IA64

From: "Zhang, Xiantao" <xiantao.zhang@intel.com>
To: Avi Kivity <avi@redhat.com>, "tgingold@free.fr" <tgingold@free.fr>
Cc: "Zhang, Yang" <yang.zhang@intel.com>,
	"kvm-ia64@vger.kernel.org" <kvm-ia64@vger.kernel.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: RE: [PATCH] KVM: Qemu: Flush i-cache after ide-dma operation in IA64
Date: Fri, 3 Apr 2009 09:22:27 +0800	[thread overview]
Message-ID: <706158FABBBA044BAD4FE898A02E4BC2326A0CBA@pdsmsx503.ccr.corp.intel.com> (raw)
In-Reply-To: <49D4E0E4.90606@redhat.com>

Avi Kivity wrote:
> Avi Kivity wrote:
>>>> 
>>> 
>>> It doesn't had to do it.  The PCI transaction will automatically
>>> invalidate caches - but qemu doesn't emulate this (and doesn't need
>>> to do on x86). 
>>> 
>> 
>> So any DMA on ia64 will flush the instruction caches?!
>> 
> 
> Or maybe, the host kernel will do it after the transaction completes?

Host kernel doesn't do anything about cache flush after DMA, since it thinks platform guarantees that. 

> In our case the lack of zero-copy means the host is invalidating the
> wrong addresses (memcpy source) and leaving the real destination
> intact. 

We just need to sync the target address(destination address), because only its physical address belongs to guest, and likely to be the DMA target address of guest. 

Xiantao