From: Andrzej Hajda <andrzej.hajda@intel.com> To: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: "Andi Shyti" <andi.shyti@intel.com>, "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, "David Airlie" <airlied@linux.ie>, dri-devel@lists.freedesktop.org, "Lucas De Marchi" <lucas.demarchi@intel.com>, linux-kernel@vger.kernel.org, "Chris Wilson" <chris.p.wilson@intel.com>, "Rodrigo Vivi" <rodrigo.vivi@intel.com>, "Dave Airlie" <airlied@redhat.com>, stable@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/gt: Serialize TLB invalidates with GT resets Date: Thu, 7 Jul 2022 23:28:18 +0200 [thread overview] Message-ID: <70a63b2e-23f5-9bf8-f782-5941f5cd01fc@intel.com> (raw) In-Reply-To: <3ecc1f94290a66b2e682f956b5232b4903c32a2c.1656921701.git.mchehab@kernel.org> On 04.07.2022 10:09, Mauro Carvalho Chehab wrote: > From: Chris Wilson <chris.p.wilson@intel.com> > > Avoid trying to invalidate the TLB in the middle of performing an > engine reset, as this may result in the reset timing out. Currently, > the TLB invalidate is only serialised by its own mutex, forgoing the > uncore lock, but we can take the uncore->lock as well to serialise > the mmio access, thereby serialising with the GDRST. > > Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with > i915 selftest/hangcheck. > > Cc: stable@vger.kernel.org # Up to 4.4 > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > Reported-by: Mauro Carvalho Chehab <mchehab@kernel.org> > Tested-by: Mauro Carvalho Chehab <mchehab@kernel.org> > Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org> > Cc: Chris Wilson <chris.p.wilson@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> > Cc: Andi Shyti <andi.shyti@intel.com> > Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > --- > > To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. > See [PATCH v3 0/2] at: https://lore.kernel.org/all/cover.1656921701.git.mchehab@kernel.org/ > > drivers/gpu/drm/i915/gt/intel_gt.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 8da3314bb6bf..68c2b0d8f187 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -952,6 +952,20 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > mutex_lock(>->tlb_invalidate_lock); > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); > > + spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */ > + > + for_each_engine(engine, gt, id) { > + struct reg_and_bit rb; > + > + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > + if (!i915_mmio_reg_offset(rb.reg)) > + continue; > + > + intel_uncore_write_fw(uncore, rb.reg, rb.bit); > + } > + > + spin_unlock_irq(&uncore->lock); > + > for_each_engine(engine, gt, id) { > /* > * HW architecture suggest typical invalidation time at 40us, > @@ -966,7 +980,6 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > if (!i915_mmio_reg_offset(rb.reg)) > continue; > > - intel_uncore_write_fw(uncore, rb.reg, rb.bit); > if (__intel_wait_for_register_fw(uncore, > rb.reg, rb.bit, 0, > timeout_us, timeout_ms,
WARNING: multiple messages have this Message-ID (diff)
From: Andrzej Hajda <andrzej.hajda@intel.com> To: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, "Andi Shyti" <andi.shyti@intel.com>, "David Airlie" <airlied@linux.ie>, intel-gfx@lists.freedesktop.org, "Lucas De Marchi" <lucas.demarchi@intel.com>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, "Chris Wilson" <chris.p.wilson@intel.com>, "Rodrigo Vivi" <rodrigo.vivi@intel.com>, "Dave Airlie" <airlied@redhat.com>, stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/gt: Serialize TLB invalidates with GT resets Date: Thu, 7 Jul 2022 23:28:18 +0200 [thread overview] Message-ID: <70a63b2e-23f5-9bf8-f782-5941f5cd01fc@intel.com> (raw) In-Reply-To: <3ecc1f94290a66b2e682f956b5232b4903c32a2c.1656921701.git.mchehab@kernel.org> On 04.07.2022 10:09, Mauro Carvalho Chehab wrote: > From: Chris Wilson <chris.p.wilson@intel.com> > > Avoid trying to invalidate the TLB in the middle of performing an > engine reset, as this may result in the reset timing out. Currently, > the TLB invalidate is only serialised by its own mutex, forgoing the > uncore lock, but we can take the uncore->lock as well to serialise > the mmio access, thereby serialising with the GDRST. > > Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with > i915 selftest/hangcheck. > > Cc: stable@vger.kernel.org # Up to 4.4 > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > Reported-by: Mauro Carvalho Chehab <mchehab@kernel.org> > Tested-by: Mauro Carvalho Chehab <mchehab@kernel.org> > Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org> > Cc: Chris Wilson <chris.p.wilson@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> > Cc: Andi Shyti <andi.shyti@intel.com> > Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > --- > > To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. > See [PATCH v3 0/2] at: https://lore.kernel.org/all/cover.1656921701.git.mchehab@kernel.org/ > > drivers/gpu/drm/i915/gt/intel_gt.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 8da3314bb6bf..68c2b0d8f187 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -952,6 +952,20 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > mutex_lock(>->tlb_invalidate_lock); > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); > > + spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */ > + > + for_each_engine(engine, gt, id) { > + struct reg_and_bit rb; > + > + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > + if (!i915_mmio_reg_offset(rb.reg)) > + continue; > + > + intel_uncore_write_fw(uncore, rb.reg, rb.bit); > + } > + > + spin_unlock_irq(&uncore->lock); > + > for_each_engine(engine, gt, id) { > /* > * HW architecture suggest typical invalidation time at 40us, > @@ -966,7 +980,6 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > if (!i915_mmio_reg_offset(rb.reg)) > continue; > > - intel_uncore_write_fw(uncore, rb.reg, rb.bit); > if (__intel_wait_for_register_fw(uncore, > rb.reg, rb.bit, 0, > timeout_us, timeout_ms,
next prev parent reply other threads:[~2022-07-07 21:28 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-04 8:09 [PATCH v3 0/2] Fix TLB invalidate issues with Broadwell Mauro Carvalho Chehab 2022-07-04 15:20 ` Mauro Carvalho Chehab 2022-07-04 15:20 ` [Intel-gfx] " Mauro Carvalho Chehab 2022-07-04 15:20 ` Mauro Carvalho Chehab 2022-07-04 8:09 ` Mauro Carvalho Chehab 2022-07-04 8:09 ` [Intel-gfx] " Mauro Carvalho Chehab 2022-07-04 8:09 ` [PATCH v3 1/2] drm/i915/gt: Serialize GRDOM access between multiple engine resets Mauro Carvalho Chehab 2022-07-04 15:20 ` [Intel-gfx] " Mauro Carvalho Chehab 2022-07-04 15:20 ` Mauro Carvalho Chehab 2022-07-04 15:20 ` Mauro Carvalho Chehab 2022-07-04 8:09 ` Mauro Carvalho Chehab 2022-07-04 8:09 ` [Intel-gfx] " Mauro Carvalho Chehab 2022-07-06 10:51 ` Andi Shyti 2022-07-06 10:51 ` [Intel-gfx] " Andi Shyti 2022-07-06 10:51 ` Andi Shyti 2022-07-07 21:27 ` [Intel-gfx] " Andrzej Hajda 2022-07-07 21:27 ` Andrzej Hajda 2022-07-04 8:09 ` [PATCH v3 2/2] drm/i915/gt: Serialize TLB invalidates with GT resets Mauro Carvalho Chehab 2022-07-04 15:20 ` Mauro Carvalho Chehab 2022-07-04 15:20 ` [Intel-gfx] " Mauro Carvalho Chehab 2022-07-04 15:20 ` Mauro Carvalho Chehab 2022-07-04 8:09 ` [Intel-gfx] " Mauro Carvalho Chehab 2022-07-04 8:09 ` Mauro Carvalho Chehab 2022-07-06 10:50 ` Andi Shyti 2022-07-06 10:50 ` [Intel-gfx] " Andi Shyti 2022-07-06 10:50 ` Andi Shyti 2022-07-07 21:28 ` Andrzej Hajda [this message] 2022-07-07 21:28 ` [Intel-gfx] " Andrzej Hajda 2022-07-04 19:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix TLB invalidate issues with Broadwell (rev3) Patchwork 2022-07-04 19:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-07-04 19:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-07-05 0:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-07-07 14:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix TLB invalidate issues with Broadwell (rev4) Patchwork 2022-07-08 14:27 ` Rodrigo Vivi 2022-07-07 14:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-07-08 14:29 ` Rodrigo Vivi 2022-07-11 6:16 ` Mauro Carvalho Chehab 2022-07-07 15:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-07-08 6:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-07-08 14:31 ` Rodrigo Vivi 2022-07-11 6:31 ` Mauro Carvalho Chehab
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=70a63b2e-23f5-9bf8-f782-5941f5cd01fc@intel.com \ --to=andrzej.hajda@intel.com \ --cc=airlied@linux.ie \ --cc=airlied@redhat.com \ --cc=andi.shyti@intel.com \ --cc=chris.p.wilson@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=linux-kernel@vger.kernel.org \ --cc=lucas.demarchi@intel.com \ --cc=mchehab@kernel.org \ --cc=rodrigo.vivi@intel.com \ --cc=stable@vger.kernel.org \ --cc=thomas.hellstrom@linux.intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.