From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: Irui Wang <irui.wang@mediatek.com>, Hans Verkuil <hverkuil-cisco@xs4all.nl>, Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Tzung-Bi Shih <tzungbi@chromium.org>, nicolas.dufresne@collabora.com, wenst@chromium.org Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Tomasz Figa <tfiga@chromium.org>, xia.jiang@mediatek.com, maoguang.meng@mediatek.com, kyrie wu <kyrie.wu@mediatek.com>, srv_heupstream@mediatek.com Subject: Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Date: Tue, 5 Jul 2022 15:00:14 +0200 [thread overview] Message-ID: <7d5986ad-40a4-f15b-8d14-aad5248379b3@collabora.com> (raw) In-Reply-To: <20220627025540.8901-2-irui.wang@mediatek.com> Il 27/06/22 04:55, Irui Wang ha scritto: > From: kyrie wu <kyrie.wu@mediatek.com> > > Add mediatek,mt8195-jpgdec compatible to binding document. > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > --- > .../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++ > 1 file changed, 176 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > new file mode 100644 > index 000000000000..8a255e8e2e09 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > @@ -0,0 +1,176 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + ...snip... > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/power/mt8195-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgdec_master { Additionally to Rob's review, which I of course fully agree on, this example devicetree does *not* work on MT8195. [ 13.015716] mtk-jpegdec-hw 1a040000.jpgdec: Adding to iommu group 1 [ 13.025383] mtk-jpegdec-hw 1a050000.jpgdec: Adding to iommu group 1 [ 13.034814] mtk-jpegdec-hw 1b040000.jpgdec: Adding to iommu group 1 [ 13.041672] mtk-jpeg soc:jpgdec_master: invalid resource [ 13.049758] mtk-jpeg: probe of soc:jpgdec_master failed with error -22 Regards, Angelo > + compatible = "mediatek,mt8195-jpgdec"; > + mediatek,jpegdec-multi-core; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; > + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + jpgdec@1a040000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ > + hw_id = <0>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_JPGDEC>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; > + }; > + > + jpgdec@1a050000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ > + hw_id = <1>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_JPGDEC_C1>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; > + }; > + > + jpgdec@1b040000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ > + hw_id = <2>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; > + }; > + }; > + };
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: Irui Wang <irui.wang@mediatek.com>, Hans Verkuil <hverkuil-cisco@xs4all.nl>, Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Tzung-Bi Shih <tzungbi@chromium.org>, nicolas.dufresne@collabora.com, wenst@chromium.org Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Tomasz Figa <tfiga@chromium.org>, xia.jiang@mediatek.com, maoguang.meng@mediatek.com, kyrie wu <kyrie.wu@mediatek.com>, srv_heupstream@mediatek.com Subject: Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Date: Tue, 5 Jul 2022 15:00:14 +0200 [thread overview] Message-ID: <7d5986ad-40a4-f15b-8d14-aad5248379b3@collabora.com> (raw) In-Reply-To: <20220627025540.8901-2-irui.wang@mediatek.com> Il 27/06/22 04:55, Irui Wang ha scritto: > From: kyrie wu <kyrie.wu@mediatek.com> > > Add mediatek,mt8195-jpgdec compatible to binding document. > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > --- > .../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++ > 1 file changed, 176 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > new file mode 100644 > index 000000000000..8a255e8e2e09 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > @@ -0,0 +1,176 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + ...snip... > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/power/mt8195-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgdec_master { Additionally to Rob's review, which I of course fully agree on, this example devicetree does *not* work on MT8195. [ 13.015716] mtk-jpegdec-hw 1a040000.jpgdec: Adding to iommu group 1 [ 13.025383] mtk-jpegdec-hw 1a050000.jpgdec: Adding to iommu group 1 [ 13.034814] mtk-jpegdec-hw 1b040000.jpgdec: Adding to iommu group 1 [ 13.041672] mtk-jpeg soc:jpgdec_master: invalid resource [ 13.049758] mtk-jpeg: probe of soc:jpgdec_master failed with error -22 Regards, Angelo > + compatible = "mediatek,mt8195-jpgdec"; > + mediatek,jpegdec-multi-core; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; > + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + jpgdec@1a040000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ > + hw_id = <0>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_JPGDEC>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; > + }; > + > + jpgdec@1a050000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ > + hw_id = <1>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_JPGDEC_C1>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; > + }; > + > + jpgdec@1b040000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ > + hw_id = <2>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; > + }; > + }; > + }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-07-05 13:39 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-07-01 15:29 ` Rob Herring 2022-07-01 15:29 ` Rob Herring 2022-07-14 8:42 ` kyrie.wu 2022-07-14 8:42 ` kyrie.wu 2022-07-05 13:00 ` AngeloGioacchino Del Regno [this message] 2022-07-05 13:00 ` AngeloGioacchino Del Regno 2022-07-14 8:56 ` kyrie.wu 2022-07-14 8:56 ` kyrie.wu 2022-06-27 2:55 ` [V4,2/8] media: mtk-jpegdec: export jpeg decoder functions Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-06-27 2:55 ` [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-07-05 13:36 ` AngeloGioacchino Del Regno 2022-07-05 13:36 ` AngeloGioacchino Del Regno 2022-07-14 8:55 ` kyrie.wu 2022-07-14 8:55 ` kyrie.wu 2022-06-27 2:55 ` [V4,4/8] media: mtk-jpegdec: add jpegdec timeout func interface Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-06-27 2:55 ` [V4,5/8] media: mtk-jpegdec: add jpeg decode worker interface Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-06-27 2:55 ` [V4,6/8] media: mtk-jpegdec: add output pic reorder interface Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-06-27 2:55 ` [V4,7/8] media: mtk-jpegdec: refactor jpegdec func interface Irui Wang 2022-06-27 2:55 ` Irui Wang 2022-06-27 2:55 ` [V4,8/8] mtk-jpegdec: add stop cmd interface for jpgdec Irui Wang 2022-06-27 2:55 ` Irui Wang
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