All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kevin Hilman <khilman@baylibre.com>
To: Jianxin Pan <jianxin.pan@amlogic.com>, linux-amlogic@lists.infradead.org
Cc: Jianxin Pan <jianxin.pan@amlogic.com>,
	Rob Herring <robh+dt@kernel.org>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	Jian Hu <jian.hu@amlogic.com>,
	Hanjie Lin <hanjie.lin@amlogic.com>,
	Victor Wan <victor.wan@amlogic.com>,
	Xingyu Chen <xingyu.chen@amlogic.com>
Subject: Re: [PATCH v5 0/4] arm64: meson: add support for A1 Power Domains
Date: Mon, 13 Jan 2020 15:40:21 -0800	[thread overview]
Message-ID: <7h7e1vdixm.fsf@baylibre.com> (raw)
In-Reply-To: <1573532930-39505-1-git-send-email-jianxin.pan@amlogic.com>

Jianxin Pan <jianxin.pan@amlogic.com> writes:

> This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power
> controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD
> and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF
> by smc.
>
> Changes since v4 at [3]:                                                         
>  - add SM_A1_ prefix for PWRC_SET/GET
>  - rename variable and update comments

Thanks for those updates

After the bindings issues are worked out, this is ready for merge.

Kevin

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Jianxin Pan <jianxin.pan@amlogic.com>, linux-amlogic@lists.infradead.org
Cc: devicetree@vger.kernel.org, Hanjie Lin <hanjie.lin@amlogic.com>,
	Victor Wan <victor.wan@amlogic.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	linux-pm@vger.kernel.org,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Jian Hu <jian.hu@amlogic.com>,
	Xingyu Chen <xingyu.chen@amlogic.com>,
	linux-arm-kernel@lists.infradead.org,
	Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH v5 0/4] arm64: meson: add support for A1 Power Domains
Date: Mon, 13 Jan 2020 15:40:21 -0800	[thread overview]
Message-ID: <7h7e1vdixm.fsf@baylibre.com> (raw)
In-Reply-To: <1573532930-39505-1-git-send-email-jianxin.pan@amlogic.com>

Jianxin Pan <jianxin.pan@amlogic.com> writes:

> This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power
> controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD
> and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF
> by smc.
>
> Changes since v4 at [3]:                                                         
>  - add SM_A1_ prefix for PWRC_SET/GET
>  - rename variable and update comments

Thanks for those updates

After the bindings issues are worked out, this is ready for merge.

Kevin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Jianxin Pan <jianxin.pan@amlogic.com>, linux-amlogic@lists.infradead.org
Cc: devicetree@vger.kernel.org, Hanjie Lin <hanjie.lin@amlogic.com>,
	Victor Wan <victor.wan@amlogic.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	linux-pm@vger.kernel.org,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Jian Hu <jian.hu@amlogic.com>,
	Xingyu Chen <xingyu.chen@amlogic.com>,
	linux-arm-kernel@lists.infradead.org,
	Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH v5 0/4] arm64: meson: add support for A1 Power Domains
Date: Mon, 13 Jan 2020 15:40:21 -0800	[thread overview]
Message-ID: <7h7e1vdixm.fsf@baylibre.com> (raw)
In-Reply-To: <1573532930-39505-1-git-send-email-jianxin.pan@amlogic.com>

Jianxin Pan <jianxin.pan@amlogic.com> writes:

> This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power
> controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD
> and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF
> by smc.
>
> Changes since v4 at [3]:                                                         
>  - add SM_A1_ prefix for PWRC_SET/GET
>  - rename variable and update comments

Thanks for those updates

After the bindings issues are worked out, this is ready for merge.

Kevin

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

  parent reply	other threads:[~2020-01-13 23:40 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-12  4:28 [PATCH v5 0/4] arm64: meson: add support for A1 Power Domains Jianxin Pan
2019-11-12  4:28 ` Jianxin Pan
2019-11-12  4:28 ` Jianxin Pan
2019-11-12  4:28 ` [PATCH v5 1/4] dt-bindings: power: add Amlogic secure power domains bindings Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2020-01-13 23:37   ` Kevin Hilman
2020-01-13 23:37     ` Kevin Hilman
2020-01-13 23:37     ` Kevin Hilman
2020-01-14  3:11     ` Jianxin Pan
2020-01-14  3:11       ` Jianxin Pan
2020-01-14  3:11       ` Jianxin Pan
2019-11-12  4:28 ` [PATCH v5 2/4] firmware: meson_sm: Add secure power domain support Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2019-11-12  4:28 ` [PATCH v5 3/4] soc: amlogic: Add support for Secure power domains controller Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2019-11-12  4:28 ` [PATCH v5 4/4] arm64: dts: meson: a1: add secure power domain controller Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2019-11-12  4:28   ` Jianxin Pan
2020-01-13 23:40 ` Kevin Hilman [this message]
2020-01-13 23:40   ` [PATCH v5 0/4] arm64: meson: add support for A1 Power Domains Kevin Hilman
2020-01-13 23:40   ` Kevin Hilman

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=7h7e1vdixm.fsf@baylibre.com \
    --to=khilman@baylibre.com \
    --cc=devicetree@vger.kernel.org \
    --cc=hanjie.lin@amlogic.com \
    --cc=jbrunet@baylibre.com \
    --cc=jian.hu@amlogic.com \
    --cc=jianxin.pan@amlogic.com \
    --cc=linux-amlogic@lists.infradead.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=martin.blumenstingl@googlemail.com \
    --cc=narmstrong@baylibre.com \
    --cc=robh+dt@kernel.org \
    --cc=victor.wan@amlogic.com \
    --cc=xingyu.chen@amlogic.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.