From: Kevin Hilman <khilman@baylibre.com>
To: Lucas Tanure <tanure@linux.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Lucas Tanure <tanure@linux.com>
Subject: Re: [PATCH 0/3] Ensure Low period of SCL is correct
Date: Mon, 28 Mar 2022 13:37:52 -0700 [thread overview]
Message-ID: <7hee2lu82n.fsf@baylibre.com> (raw)
In-Reply-To: <20220326102229.421718-1-tanure@linux.com>
Hi Lucas,
Lucas Tanure <tanure@linux.com> writes:
> The default duty cycle of 33% is less than the required
> by the I2C specs for the LOW period of the SCL clock.
>
> So, for 100Khz or less, use 50%H/50%L duty cycle, and
> for the clock above 100Khz, use 40%H/60%L duty cycle.
> That ensures the low period of SCL is always more than
> the minimum required by the specs at any given frequency.
Thanks for the fixes!
This is going to affect all SoCs, so ould you please summarize how your
changes were tested, and on which SoCs & boards?
Thanks,
Kevin
WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Lucas Tanure <tanure@linux.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Lucas Tanure <tanure@linux.com>
Subject: Re: [PATCH 0/3] Ensure Low period of SCL is correct
Date: Mon, 28 Mar 2022 13:37:52 -0700 [thread overview]
Message-ID: <7hee2lu82n.fsf@baylibre.com> (raw)
In-Reply-To: <20220326102229.421718-1-tanure@linux.com>
Hi Lucas,
Lucas Tanure <tanure@linux.com> writes:
> The default duty cycle of 33% is less than the required
> by the I2C specs for the LOW period of the SCL clock.
>
> So, for 100Khz or less, use 50%H/50%L duty cycle, and
> for the clock above 100Khz, use 40%H/60%L duty cycle.
> That ensures the low period of SCL is always more than
> the minimum required by the specs at any given frequency.
Thanks for the fixes!
This is going to affect all SoCs, so ould you please summarize how your
changes were tested, and on which SoCs & boards?
Thanks,
Kevin
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Lucas Tanure <tanure@linux.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Lucas Tanure <tanure@linux.com>
Subject: Re: [PATCH 0/3] Ensure Low period of SCL is correct
Date: Mon, 28 Mar 2022 13:37:52 -0700 [thread overview]
Message-ID: <7hee2lu82n.fsf@baylibre.com> (raw)
In-Reply-To: <20220326102229.421718-1-tanure@linux.com>
Hi Lucas,
Lucas Tanure <tanure@linux.com> writes:
> The default duty cycle of 33% is less than the required
> by the I2C specs for the LOW period of the SCL clock.
>
> So, for 100Khz or less, use 50%H/50%L duty cycle, and
> for the clock above 100Khz, use 40%H/60%L duty cycle.
> That ensures the low period of SCL is always more than
> the minimum required by the specs at any given frequency.
Thanks for the fixes!
This is going to affect all SoCs, so ould you please summarize how your
changes were tested, and on which SoCs & boards?
Thanks,
Kevin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-03-28 20:37 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-26 10:22 [PATCH 0/3] Ensure Low period of SCL is correct Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-26 10:22 ` [PATCH 1/3] i2c: meson: Use _SHIFT and _MASK for register definitions Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-26 10:22 ` [PATCH 2/3] i2c: meson: Use 50% duty cycle for I2C clock Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-04-05 9:30 ` Neil Armstrong
2022-04-05 9:30 ` Neil Armstrong
2022-04-05 9:30 ` Neil Armstrong
2022-04-06 11:31 ` Neil Armstrong
2022-04-06 11:31 ` Neil Armstrong
2022-04-06 11:31 ` Neil Armstrong
2022-04-08 7:18 ` Lucas Tanure
2022-04-08 7:18 ` Lucas Tanure
2022-04-08 7:18 ` Lucas Tanure
2022-03-26 10:22 ` [PATCH 3/3] i2c: meson: Remove meson_i2c_data Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-26 10:22 ` Lucas Tanure
2022-03-28 20:37 ` Kevin Hilman [this message]
2022-03-28 20:37 ` [PATCH 0/3] Ensure Low period of SCL is correct Kevin Hilman
2022-03-28 20:37 ` Kevin Hilman
2022-03-28 22:31 ` Lucas Tanure
2022-03-28 22:31 ` Lucas Tanure
2022-03-28 22:31 ` Lucas Tanure
2022-04-04 8:01 ` Neil Armstrong
2022-04-04 8:01 ` Neil Armstrong
2022-04-04 8:01 ` Neil Armstrong
2022-04-04 18:00 ` Vyacheslav
2022-04-04 18:00 ` Vyacheslav
2022-04-04 18:00 ` Vyacheslav
[not found] ` <CAJX_Q+1Y5pO_AGaFSXfo-J3EdGQeM2XYXzvsUtjtAFEXdwKEdQ@mail.gmail.com>
2022-04-05 15:11 ` Neil Armstrong
2022-04-05 15:11 ` Neil Armstrong
2022-04-05 15:11 ` Neil Armstrong
2022-04-08 7:19 ` Lucas Tanure
2022-04-08 7:19 ` Lucas Tanure
2022-04-08 7:19 ` Lucas Tanure
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