From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
michal.simek@xilinx.com, git@xilinx.com
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 05/12] arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
Date: Thu, 21 Jan 2021 11:26:53 +0100 [thread overview]
Message-ID: <80b52ef97501968ee97fc152363bc4b9b7bb2cff.1611224800.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1611224800.git.michal.simek@xilinx.com>
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 +++++++
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 28 +++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 10 +++++++
.../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 10 +++++++
4 files changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 68c2ad30d62d..d92698ffbf8c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
@@ -663,6 +664,13 @@ &pcie {
status = "okay";
};
+&psgtr {
+ status = "okay";
+ /* pcie, sata, usb3, dp */
+ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref0", "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
@@ -678,6 +686,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 7a4614e3f5fa..5e2be9abc175 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU104 RevA";
@@ -36,6 +37,24 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ clock_8t49n287_5: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clock_8t49n287_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clock_8t49n287_3: clk27 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
};
&can1 {
@@ -158,6 +177,13 @@ &rtc {
status = "okay";
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&sata {
status = "okay";
/* SATA OOB timing settings */
@@ -169,6 +195,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index a29ff20090ce..4ec6715abab7 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU106 RevA";
@@ -658,6 +659,13 @@ i2c@7 {
};
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
@@ -673,6 +681,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index 92b3cee62d11..2969c4b71384 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU111 RevA";
@@ -541,6 +542,13 @@ i2c@7 {
};
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
@@ -556,6 +564,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
--
2.30.0
WARNING: multiple messages have this Message-ID (diff)
From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
michal.simek@xilinx.com, git@xilinx.com
Cc: devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v2 05/12] arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
Date: Thu, 21 Jan 2021 11:26:53 +0100 [thread overview]
Message-ID: <80b52ef97501968ee97fc152363bc4b9b7bb2cff.1611224800.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1611224800.git.michal.simek@xilinx.com>
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 +++++++
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 28 +++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 10 +++++++
.../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 10 +++++++
4 files changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 68c2ad30d62d..d92698ffbf8c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
@@ -663,6 +664,13 @@ &pcie {
status = "okay";
};
+&psgtr {
+ status = "okay";
+ /* pcie, sata, usb3, dp */
+ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref0", "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
@@ -678,6 +686,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 7a4614e3f5fa..5e2be9abc175 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU104 RevA";
@@ -36,6 +37,24 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ clock_8t49n287_5: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clock_8t49n287_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clock_8t49n287_3: clk27 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
};
&can1 {
@@ -158,6 +177,13 @@ &rtc {
status = "okay";
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&sata {
status = "okay";
/* SATA OOB timing settings */
@@ -169,6 +195,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index a29ff20090ce..4ec6715abab7 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU106 RevA";
@@ -658,6 +659,13 @@ i2c@7 {
};
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
@@ -673,6 +681,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index 92b3cee62d11..2969c4b71384 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU111 RevA";
@@ -541,6 +542,13 @@ i2c@7 {
};
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
@@ -556,6 +564,8 @@ &sata {
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
--
2.30.0
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next prev parent reply other threads:[~2021-01-21 18:05 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 10:26 [PATCH v2 00/12] arm64: dts: zynqmp: DT updates to match latest drivers Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 01/12] arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 02/12] arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 03/12] arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 04/12] arm64: dts: zynqmp: Enable reset controller driver Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 22:38 ` Laurent Pinchart
2021-01-21 22:38 ` Laurent Pinchart
2021-01-21 10:26 ` Michal Simek [this message]
2021-01-21 10:26 ` [PATCH v2 05/12] arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 Michal Simek
2021-01-21 10:26 ` [PATCH v2 06/12] arm64: dts: zynqmp: Add label for zynqmp_ipi Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 07/12] arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 08/12] arm64: dts: zynqmp: Wire arasan nand controller Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 09/12] arm64: dts: zynqmp: Wire zynqmp qspi controller Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 10/12] arm64: dts: zynqmp: Add missing lpd watchdog node Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 11/12] arm64: dts: zynqmp: Add missing iommu IDs Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:27 ` [PATCH v2 12/12] arm64: dts: zynqmp: Add description for zcu104 revC Michal Simek
2021-01-21 10:27 ` Michal Simek
2021-02-01 9:38 ` Michal Simek
2021-02-01 9:38 ` Michal Simek
2021-02-01 9:36 ` [PATCH v2 00/12] arm64: dts: zynqmp: DT updates to match latest drivers Michal Simek
2021-02-01 9:36 ` Michal Simek
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