From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: x86 <x86@kernel.org>, Dave Hansen <dave.hansen@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-mm <linux-mm@kvack.org>,
Andrew Morton <akpm@linux-foundation.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
Nicholas Piggin <npiggin@gmail.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
stable <stable@vger.kernel.org>
Subject: Re: [PATCH 8/8] membarrier: Rewrite sync_core_before_usermode() and improve documentation
Date: Thu, 17 Jun 2021 10:47:57 -0400 (EDT) [thread overview]
Message-ID: <827549827.10547.1623941277868.JavaMail.zimbra@efficios.com> (raw)
In-Reply-To: <07a8b963002cb955b7516e61bad19514a3acaa82.1623813516.git.luto@kernel.org>
----- On Jun 15, 2021, at 11:21 PM, Andy Lutomirski luto@kernel.org wrote:
> The old sync_core_before_usermode() comments suggested that a non-icache-syncing
> return-to-usermode instruction is x86-specific and that all other
> architectures automatically notice cross-modified code on return to
> userspace.
>
> This is misleading. The incantation needed to modify code from one
> CPU and execute it on another CPU is highly architecture dependent.
> On x86, according to the SDM, one must modify the code, issue SFENCE
> if the modification was WC or nontemporal, and then issue a "serializing
> instruction" on the CPU that will execute the code. membarrier() can do
> the latter.
>
> On arm64 and powerpc, one must flush the icache and then flush the pipeline
> on the target CPU, although the CPU manuals don't necessarily use this
> language.
>
> So let's drop any pretense that we can have a generic way to define or
> implement membarrier's SYNC_CORE operation and instead require all
> architectures to define the helper and supply their own documentation as to
> how to use it.
Agreed. Documentation of the sequence of operations that need to be performed
when cross-modifying code on SMP should be per-architecture. The documentation
of the architectural effects of membarrier sync-core should be per-arch as well.
> This means x86, arm64, and powerpc for now.
And also arm32, as discussed in the other leg of the patchset's email thread.
> Let's also
> rename the function from sync_core_before_usermode() to
> membarrier_sync_core_before_usermode() because the precise flushing details
> may very well be specific to membarrier, and even the concept of
> "sync_core" in the kernel is mostly an x86-ism.
OK
>
[...]
>
> static void ipi_rseq(void *info)
> {
> @@ -368,12 +373,14 @@ static int membarrier_private_expedited(int flags, int
> cpu_id)
> smp_call_func_t ipi_func = ipi_mb;
>
> if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
> - if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
> +#ifndef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
> return -EINVAL;
> +#else
> if (!(atomic_read(&mm->membarrier_state) &
> MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
> return -EPERM;
> ipi_func = ipi_sync_core;
> +#endif
Please change back this #ifndef / #else / #endif within function for
if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE)) {
...
} else {
...
}
I don't think mixing up preprocessor and code logic makes it more readable.
Thanks,
Mathieu
> } else if (flags == MEMBARRIER_FLAG_RSEQ) {
> if (!IS_ENABLED(CONFIG_RSEQ))
> return -EINVAL;
> --
> 2.31.1
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, linux-mm <linux-mm@kvack.org>,
Peter Zijlstra <peterz@infradead.org>, x86 <x86@kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Nicholas Piggin <npiggin@gmail.com>,
Dave Hansen <dave.hansen@intel.com>,
Paul Mackerras <paulus@samba.org>,
stable <stable@vger.kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 8/8] membarrier: Rewrite sync_core_before_usermode() and improve documentation
Date: Thu, 17 Jun 2021 10:47:57 -0400 (EDT) [thread overview]
Message-ID: <827549827.10547.1623941277868.JavaMail.zimbra@efficios.com> (raw)
In-Reply-To: <07a8b963002cb955b7516e61bad19514a3acaa82.1623813516.git.luto@kernel.org>
----- On Jun 15, 2021, at 11:21 PM, Andy Lutomirski luto@kernel.org wrote:
> The old sync_core_before_usermode() comments suggested that a non-icache-syncing
> return-to-usermode instruction is x86-specific and that all other
> architectures automatically notice cross-modified code on return to
> userspace.
>
> This is misleading. The incantation needed to modify code from one
> CPU and execute it on another CPU is highly architecture dependent.
> On x86, according to the SDM, one must modify the code, issue SFENCE
> if the modification was WC or nontemporal, and then issue a "serializing
> instruction" on the CPU that will execute the code. membarrier() can do
> the latter.
>
> On arm64 and powerpc, one must flush the icache and then flush the pipeline
> on the target CPU, although the CPU manuals don't necessarily use this
> language.
>
> So let's drop any pretense that we can have a generic way to define or
> implement membarrier's SYNC_CORE operation and instead require all
> architectures to define the helper and supply their own documentation as to
> how to use it.
Agreed. Documentation of the sequence of operations that need to be performed
when cross-modifying code on SMP should be per-architecture. The documentation
of the architectural effects of membarrier sync-core should be per-arch as well.
> This means x86, arm64, and powerpc for now.
And also arm32, as discussed in the other leg of the patchset's email thread.
> Let's also
> rename the function from sync_core_before_usermode() to
> membarrier_sync_core_before_usermode() because the precise flushing details
> may very well be specific to membarrier, and even the concept of
> "sync_core" in the kernel is mostly an x86-ism.
OK
>
[...]
>
> static void ipi_rseq(void *info)
> {
> @@ -368,12 +373,14 @@ static int membarrier_private_expedited(int flags, int
> cpu_id)
> smp_call_func_t ipi_func = ipi_mb;
>
> if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
> - if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
> +#ifndef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
> return -EINVAL;
> +#else
> if (!(atomic_read(&mm->membarrier_state) &
> MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
> return -EPERM;
> ipi_func = ipi_sync_core;
> +#endif
Please change back this #ifndef / #else / #endif within function for
if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE)) {
...
} else {
...
}
I don't think mixing up preprocessor and code logic makes it more readable.
Thanks,
Mathieu
> } else if (flags == MEMBARRIER_FLAG_RSEQ) {
> if (!IS_ENABLED(CONFIG_RSEQ))
> return -EINVAL;
> --
> 2.31.1
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: x86 <x86@kernel.org>, Dave Hansen <dave.hansen@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-mm <linux-mm@kvack.org>,
Andrew Morton <akpm@linux-foundation.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
Nicholas Piggin <npiggin@gmail.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
stable <stable@vger.kernel.org>
Subject: Re: [PATCH 8/8] membarrier: Rewrite sync_core_before_usermode() and improve documentation
Date: Thu, 17 Jun 2021 10:47:57 -0400 (EDT) [thread overview]
Message-ID: <827549827.10547.1623941277868.JavaMail.zimbra@efficios.com> (raw)
In-Reply-To: <07a8b963002cb955b7516e61bad19514a3acaa82.1623813516.git.luto@kernel.org>
----- On Jun 15, 2021, at 11:21 PM, Andy Lutomirski luto@kernel.org wrote:
> The old sync_core_before_usermode() comments suggested that a non-icache-syncing
> return-to-usermode instruction is x86-specific and that all other
> architectures automatically notice cross-modified code on return to
> userspace.
>
> This is misleading. The incantation needed to modify code from one
> CPU and execute it on another CPU is highly architecture dependent.
> On x86, according to the SDM, one must modify the code, issue SFENCE
> if the modification was WC or nontemporal, and then issue a "serializing
> instruction" on the CPU that will execute the code. membarrier() can do
> the latter.
>
> On arm64 and powerpc, one must flush the icache and then flush the pipeline
> on the target CPU, although the CPU manuals don't necessarily use this
> language.
>
> So let's drop any pretense that we can have a generic way to define or
> implement membarrier's SYNC_CORE operation and instead require all
> architectures to define the helper and supply their own documentation as to
> how to use it.
Agreed. Documentation of the sequence of operations that need to be performed
when cross-modifying code on SMP should be per-architecture. The documentation
of the architectural effects of membarrier sync-core should be per-arch as well.
> This means x86, arm64, and powerpc for now.
And also arm32, as discussed in the other leg of the patchset's email thread.
> Let's also
> rename the function from sync_core_before_usermode() to
> membarrier_sync_core_before_usermode() because the precise flushing details
> may very well be specific to membarrier, and even the concept of
> "sync_core" in the kernel is mostly an x86-ism.
OK
>
[...]
>
> static void ipi_rseq(void *info)
> {
> @@ -368,12 +373,14 @@ static int membarrier_private_expedited(int flags, int
> cpu_id)
> smp_call_func_t ipi_func = ipi_mb;
>
> if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
> - if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
> +#ifndef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
> return -EINVAL;
> +#else
> if (!(atomic_read(&mm->membarrier_state) &
> MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
> return -EPERM;
> ipi_func = ipi_sync_core;
> +#endif
Please change back this #ifndef / #else / #endif within function for
if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE)) {
...
} else {
...
}
I don't think mixing up preprocessor and code logic makes it more readable.
Thanks,
Mathieu
> } else if (flags == MEMBARRIER_FLAG_RSEQ) {
> if (!IS_ENABLED(CONFIG_RSEQ))
> return -EINVAL;
> --
> 2.31.1
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-17 14:48 UTC|newest]
Thread overview: 165+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 3:21 [PATCH 0/8] membarrier cleanups Andy Lutomirski
2021-06-16 3:21 ` [PATCH 1/8] membarrier: Document why membarrier() works Andy Lutomirski
2021-06-16 4:00 ` Nicholas Piggin
2021-06-16 7:30 ` Peter Zijlstra
2021-06-17 23:45 ` Andy Lutomirski
2021-06-16 3:21 ` [PATCH 2/8] x86/mm: Handle unlazying membarrier core sync in the arch code Andy Lutomirski
2021-06-16 4:25 ` Nicholas Piggin
2021-06-16 18:31 ` Andy Lutomirski
2021-06-16 17:49 ` Mathieu Desnoyers
2021-06-16 17:49 ` Mathieu Desnoyers
2021-06-16 18:31 ` Andy Lutomirski
2021-06-16 3:21 ` [PATCH 3/8] membarrier: Remove membarrier_arch_switch_mm() prototype in core code Andy Lutomirski
2021-06-16 4:26 ` Nicholas Piggin
2021-06-16 17:52 ` Mathieu Desnoyers
2021-06-16 17:52 ` Mathieu Desnoyers
2021-06-16 3:21 ` [PATCH 4/8] membarrier: Make the post-switch-mm barrier explicit Andy Lutomirski
2021-06-16 4:19 ` Nicholas Piggin
2021-06-16 7:35 ` Peter Zijlstra
2021-06-16 18:41 ` Andy Lutomirski
2021-06-17 1:37 ` Nicholas Piggin
2021-06-17 2:57 ` Andy Lutomirski
2021-06-17 5:32 ` Andy Lutomirski
2021-06-17 6:51 ` Nicholas Piggin
2021-06-17 23:49 ` Andy Lutomirski
2021-06-19 2:53 ` Nicholas Piggin
2021-06-19 3:20 ` Andy Lutomirski
2021-06-19 4:27 ` Nicholas Piggin
2021-06-17 9:08 ` [RFC][PATCH] sched: Use lightweight hazard pointers to grab lazy mms Peter Zijlstra
2021-06-17 9:10 ` Peter Zijlstra
2021-06-17 10:00 ` Nicholas Piggin
2021-06-17 9:13 ` Peter Zijlstra
2021-06-17 14:06 ` Andy Lutomirski
2021-06-17 9:28 ` Peter Zijlstra
2021-06-17 14:03 ` Andy Lutomirski
2021-06-17 14:10 ` Andy Lutomirski
2021-06-17 15:45 ` Peter Zijlstra
2021-06-18 3:29 ` Paul E. McKenney
2021-06-18 5:04 ` Andy Lutomirski
2021-06-17 15:02 ` [PATCH 4/8] membarrier: Make the post-switch-mm barrier explicit Paul E. McKenney
2021-06-18 0:06 ` Andy Lutomirski
2021-06-18 3:35 ` Paul E. McKenney
2021-06-17 8:45 ` Peter Zijlstra
2021-06-16 3:21 ` [PATCH 5/8] membarrier, kthread: Use _ONCE accessors for task->mm Andy Lutomirski
2021-06-16 4:28 ` Nicholas Piggin
2021-06-16 18:08 ` Mathieu Desnoyers
2021-06-16 18:08 ` Mathieu Desnoyers
2021-06-16 18:45 ` Andy Lutomirski
2021-06-16 3:21 ` [PATCH 6/8] powerpc/membarrier: Remove special barrier on mm switch Andy Lutomirski
2021-06-16 3:21 ` Andy Lutomirski
2021-06-16 4:36 ` Nicholas Piggin
2021-06-16 4:36 ` Nicholas Piggin
2021-06-16 3:21 ` [PATCH 7/8] membarrier: Remove arm (32) support for SYNC_CORE Andy Lutomirski
2021-06-16 3:21 ` Andy Lutomirski
2021-06-16 9:28 ` Russell King (Oracle)
2021-06-16 9:28 ` Russell King (Oracle)
2021-06-16 10:16 ` Peter Zijlstra
2021-06-16 10:16 ` Peter Zijlstra
2021-06-16 10:20 ` Peter Zijlstra
2021-06-16 10:20 ` Peter Zijlstra
2021-06-16 10:34 ` Russell King (Oracle)
2021-06-16 10:34 ` Russell King (Oracle)
2021-06-16 11:10 ` Peter Zijlstra
2021-06-16 11:10 ` Peter Zijlstra
2021-06-16 13:22 ` Russell King (Oracle)
2021-06-16 13:22 ` Russell King (Oracle)
2021-06-16 15:04 ` Catalin Marinas
2021-06-16 15:04 ` Catalin Marinas
2021-06-16 15:23 ` Russell King (Oracle)
2021-06-16 15:23 ` Russell King (Oracle)
2021-06-16 15:45 ` Catalin Marinas
2021-06-16 15:45 ` Catalin Marinas
2021-06-16 16:00 ` Catalin Marinas
2021-06-16 16:00 ` Catalin Marinas
2021-06-16 16:27 ` Russell King (Oracle)
2021-06-16 16:27 ` Russell King (Oracle)
2021-06-17 8:55 ` Krzysztof Hałasa
2021-06-17 8:55 ` Krzysztof Hałasa
2021-06-17 8:55 ` Krzysztof Hałasa
2021-06-18 12:54 ` Linus Walleij
2021-06-18 12:54 ` Linus Walleij
2021-06-18 12:54 ` Linus Walleij
2021-06-18 13:19 ` Russell King (Oracle)
2021-06-18 13:19 ` Russell King (Oracle)
2021-06-18 13:36 ` Arnd Bergmann
2021-06-18 13:36 ` Arnd Bergmann
2021-06-18 13:36 ` Arnd Bergmann
2021-06-17 10:40 ` Mark Rutland
2021-06-17 10:40 ` Mark Rutland
2021-06-17 11:23 ` Russell King (Oracle)
2021-06-17 11:23 ` Russell King (Oracle)
2021-06-17 11:33 ` Mark Rutland
2021-06-17 11:33 ` Mark Rutland
2021-06-17 13:41 ` Andy Lutomirski
2021-06-17 13:41 ` Andy Lutomirski
2021-06-17 13:51 ` Mark Rutland
2021-06-17 13:51 ` Mark Rutland
2021-06-17 14:00 ` Andy Lutomirski
2021-06-17 14:00 ` Andy Lutomirski
2021-06-17 14:20 ` Mark Rutland
2021-06-17 14:20 ` Mark Rutland
2021-06-17 15:01 ` Peter Zijlstra
2021-06-17 15:01 ` Peter Zijlstra
2021-06-17 15:13 ` Peter Zijlstra
2021-06-17 15:13 ` Peter Zijlstra
2021-06-17 14:16 ` Mathieu Desnoyers
2021-06-17 14:16 ` Mathieu Desnoyers
2021-06-17 14:05 ` Peter Zijlstra
2021-06-17 14:05 ` Peter Zijlstra
2021-06-18 0:07 ` Andy Lutomirski
2021-06-18 0:07 ` Andy Lutomirski
2021-06-16 3:21 ` [PATCH 8/8] membarrier: Rewrite sync_core_before_usermode() and improve documentation Andy Lutomirski
2021-06-16 3:21 ` Andy Lutomirski
2021-06-16 3:21 ` Andy Lutomirski
2021-06-16 4:45 ` Nicholas Piggin
2021-06-16 4:45 ` Nicholas Piggin
2021-06-16 4:45 ` Nicholas Piggin
2021-06-16 18:52 ` Andy Lutomirski
2021-06-16 18:52 ` Andy Lutomirski
2021-06-16 18:52 ` Andy Lutomirski
2021-06-16 23:48 ` Andy Lutomirski
2021-06-16 23:48 ` Andy Lutomirski
2021-06-16 23:48 ` Andy Lutomirski
2021-06-18 15:27 ` Christophe Leroy
2021-06-18 15:27 ` Christophe Leroy
2021-06-18 15:27 ` Christophe Leroy
2021-06-16 10:20 ` Will Deacon
2021-06-16 10:20 ` Will Deacon
2021-06-16 10:20 ` Will Deacon
2021-06-16 23:58 ` Andy Lutomirski
2021-06-16 23:58 ` Andy Lutomirski
2021-06-16 23:58 ` Andy Lutomirski
2021-06-17 14:47 ` Mathieu Desnoyers [this message]
2021-06-17 14:47 ` Mathieu Desnoyers
2021-06-17 14:47 ` Mathieu Desnoyers
2021-06-17 14:47 ` Mathieu Desnoyers
2021-06-18 0:12 ` Andy Lutomirski
2021-06-18 0:12 ` Andy Lutomirski
2021-06-18 0:12 ` Andy Lutomirski
2021-06-18 16:31 ` Mathieu Desnoyers
2021-06-18 16:31 ` Mathieu Desnoyers
2021-06-18 16:31 ` Mathieu Desnoyers
2021-06-18 16:31 ` Mathieu Desnoyers
2021-06-18 19:58 ` Andy Lutomirski
2021-06-18 19:58 ` Andy Lutomirski
2021-06-18 19:58 ` Andy Lutomirski
2021-06-18 20:09 ` Mathieu Desnoyers
2021-06-18 20:09 ` Mathieu Desnoyers
2021-06-18 20:09 ` Mathieu Desnoyers
2021-06-18 20:09 ` Mathieu Desnoyers
2021-06-19 6:02 ` Nicholas Piggin
2021-06-19 6:02 ` Nicholas Piggin
2021-06-19 6:02 ` Nicholas Piggin
2021-06-19 15:50 ` Andy Lutomirski
2021-06-19 15:50 ` Andy Lutomirski
2021-06-19 15:50 ` Andy Lutomirski
2021-06-20 2:10 ` Nicholas Piggin
2021-06-20 2:10 ` Nicholas Piggin
2021-06-20 2:10 ` Nicholas Piggin
2021-06-17 15:16 ` Mathieu Desnoyers
2021-06-17 15:16 ` Mathieu Desnoyers
2021-06-17 15:16 ` Mathieu Desnoyers
2021-06-17 15:16 ` Mathieu Desnoyers
2021-06-18 0:13 ` Andy Lutomirski
2021-06-18 0:13 ` Andy Lutomirski
2021-06-18 0:13 ` Andy Lutomirski
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