All of lore.kernel.org
 help / color / mirror / Atom feed
From: Marc Zyngier <maz@kernel.org>
To: Yanan Wang <wangyanan55@huawei.com>
Cc: kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
	linux-kernel@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 4/6] KVM: arm64: Provide invalidate_icache_range at non-VHE EL2
Date: Wed, 02 Jun 2021 11:22:56 +0100	[thread overview]
Message-ID: <875yyw1s73.wl-maz@kernel.org> (raw)
In-Reply-To: <20210415115032.35760-5-wangyanan55@huawei.com>

On Thu, 15 Apr 2021 12:50:30 +0100,
Yanan Wang <wangyanan55@huawei.com> wrote:
> 
> We want to move I-cache maintenance for the guest to the stage-2
> page table code for performance improvement. Before it can work,
> we should first make function invalidate_icache_range available
> to non-VHE EL2 to avoid compiling or program running error, as
> pgtable.c is now linked into the non-VHE EL2 code for pKVM mode.
> 
> In this patch, we only introduce symbol of invalidate_icache_range
> with no real functionality in nvhe/cache.S, because there haven't
> been situations found currently where I-cache maintenance is also
> needed in non-VHE EL2 for pKVM mode.
> 
> Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
> ---
>  arch/arm64/kvm/hyp/nvhe/cache.S | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/kvm/hyp/nvhe/cache.S b/arch/arm64/kvm/hyp/nvhe/cache.S
> index 36cef6915428..a125ec9aeed2 100644
> --- a/arch/arm64/kvm/hyp/nvhe/cache.S
> +++ b/arch/arm64/kvm/hyp/nvhe/cache.S
> @@ -11,3 +11,14 @@ SYM_FUNC_START_PI(__flush_dcache_area)
>  	dcache_by_line_op civac, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__flush_dcache_area)
> +
> +/*
> + *	invalidate_icache_range(start,end)
> + *
> + *	Ensure that the I cache is invalid within specified region.
> + *
> + *	- start   - virtual start address of region
> + *	- end     - virtual end address of region
> + */
> +SYM_FUNC_START(invalidate_icache_range)
> +SYM_FUNC_END(invalidate_icache_range)

This is a good indication that something is really wrong.

If you were to provide cache management callbacks as part of the
mm_ops themselves (or a similar abstraction), you wouldn't have to do
these things.

	M.

-- 
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Yanan Wang <wangyanan55@huawei.com>
Cc: Will Deacon <will@kernel.org>,
	"Quentin\ Perret" <qperret@google.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	<kvmarm@lists.cs.columbia.edu>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	"Suzuki K Poulose" <suzuki.poulose@arm.com>,
	Gavin Shan <gshan@redhat.com>, <wanghaibin.wang@huawei.com>,
	<zhukeqian1@huawei.com>, <yuzenghui@huawei.com>
Subject: Re: [PATCH v5 4/6] KVM: arm64: Provide invalidate_icache_range at non-VHE EL2
Date: Wed, 02 Jun 2021 11:22:56 +0100	[thread overview]
Message-ID: <875yyw1s73.wl-maz@kernel.org> (raw)
In-Reply-To: <20210415115032.35760-5-wangyanan55@huawei.com>

On Thu, 15 Apr 2021 12:50:30 +0100,
Yanan Wang <wangyanan55@huawei.com> wrote:
> 
> We want to move I-cache maintenance for the guest to the stage-2
> page table code for performance improvement. Before it can work,
> we should first make function invalidate_icache_range available
> to non-VHE EL2 to avoid compiling or program running error, as
> pgtable.c is now linked into the non-VHE EL2 code for pKVM mode.
> 
> In this patch, we only introduce symbol of invalidate_icache_range
> with no real functionality in nvhe/cache.S, because there haven't
> been situations found currently where I-cache maintenance is also
> needed in non-VHE EL2 for pKVM mode.
> 
> Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
> ---
>  arch/arm64/kvm/hyp/nvhe/cache.S | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/kvm/hyp/nvhe/cache.S b/arch/arm64/kvm/hyp/nvhe/cache.S
> index 36cef6915428..a125ec9aeed2 100644
> --- a/arch/arm64/kvm/hyp/nvhe/cache.S
> +++ b/arch/arm64/kvm/hyp/nvhe/cache.S
> @@ -11,3 +11,14 @@ SYM_FUNC_START_PI(__flush_dcache_area)
>  	dcache_by_line_op civac, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__flush_dcache_area)
> +
> +/*
> + *	invalidate_icache_range(start,end)
> + *
> + *	Ensure that the I cache is invalid within specified region.
> + *
> + *	- start   - virtual start address of region
> + *	- end     - virtual end address of region
> + */
> +SYM_FUNC_START(invalidate_icache_range)
> +SYM_FUNC_END(invalidate_icache_range)

This is a good indication that something is really wrong.

If you were to provide cache management callbacks as part of the
mm_ops themselves (or a similar abstraction), you wouldn't have to do
these things.

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-06-02 10:23 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-15 11:50 [PATCH v5 0/6] KVM: arm64: Improve efficiency of stage2 page table Yanan Wang
2021-04-15 11:50 ` Yanan Wang
2021-04-15 11:50 ` Yanan Wang
2021-04-15 11:50 ` [PATCH v5 1/6] KVM: arm64: Introduce KVM_PGTABLE_S2_GUEST stage-2 flag Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-06-02 10:43   ` Quentin Perret
2021-06-02 10:43     ` Quentin Perret
2021-06-02 10:43     ` Quentin Perret
2021-06-03 12:36     ` wangyanan (Y)
2021-06-03 12:36       ` wangyanan (Y)
2021-06-03 12:36       ` wangyanan (Y)
2021-04-15 11:50 ` [PATCH v5 2/6] KVM: arm64: Move D-cache flush to the fault handlers Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-06-02 10:19   ` Marc Zyngier
2021-06-02 10:19     ` Marc Zyngier
2021-06-02 10:49     ` Quentin Perret
2021-06-02 10:49       ` Quentin Perret
2021-06-02 10:49       ` Quentin Perret
2021-06-03 12:33     ` wangyanan (Y)
2021-06-03 12:33       ` wangyanan (Y)
2021-06-03 12:33       ` wangyanan (Y)
2021-04-15 11:50 ` [PATCH v5 3/6] KVM: arm64: Add mm_ops member for structure stage2_attr_data Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50 ` [PATCH v5 4/6] KVM: arm64: Provide invalidate_icache_range at non-VHE EL2 Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-06-02 10:22   ` Marc Zyngier [this message]
2021-06-02 10:22     ` Marc Zyngier
2021-06-03 12:34     ` wangyanan (Y)
2021-06-03 12:34       ` wangyanan (Y)
2021-06-03 12:34       ` wangyanan (Y)
2021-04-15 11:50 ` [PATCH v5 5/6] KVM: arm64: Move I-cache flush to the fault handlers Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-06-02 10:58   ` Quentin Perret
2021-06-02 10:58     ` Quentin Perret
2021-06-02 10:58     ` Quentin Perret
2021-06-03 12:35     ` wangyanan (Y)
2021-06-03 12:35       ` wangyanan (Y)
2021-06-03 12:35       ` wangyanan (Y)
2021-04-15 11:50 ` [PATCH v5 6/6] KVM: arm64: Distinguish cases of memcache allocations completely Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-04-15 11:50   ` Yanan Wang
2021-06-02 11:07   ` Quentin Perret
2021-06-02 11:07     ` Quentin Perret
2021-06-02 11:07     ` Quentin Perret
2021-06-03 12:52     ` wangyanan (Y)
2021-06-03 12:52       ` wangyanan (Y)
2021-06-03 12:52       ` wangyanan (Y)
2021-05-12 12:54 ` [PATCH v5 0/6] KVM: arm64: Improve efficiency of stage2 page table wangyanan (Y)
2021-05-12 12:54   ` wangyanan (Y)
2021-05-12 12:54   ` wangyanan (Y)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=875yyw1s73.wl-maz@kernel.org \
    --to=maz@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=wangyanan55@huawei.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.