From: Marc Zyngier <maz@kernel.org> To: "Pali Rohár" <pali@kernel.org> Cc: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Rob Herring" <robh@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Russell King" <rmk+kernel@armlinux.org.uk>, "Marek Behún" <kabel@kernel.org>, "Remi Pommarel" <repk@triplefau.lt>, Xogium <contact@xogium.me>, "Tomasz Maciej Nowak" <tmn505@gmail.com>, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 19/42] PCI: aardvark: Fix setting MSI address Date: Fri, 07 May 2021 11:25:30 +0100 [thread overview] Message-ID: <87a6p6q1r9.wl-maz@kernel.org> (raw) In-Reply-To: <20210506153153.30454-20-pali@kernel.org> On Thu, 06 May 2021 16:31:30 +0100, Pali Rohár <pali@kernel.org> wrote: > > MSI address for receiving MSI interrupts needs to be correctly set before > enabling processing of MSI interrupts. > > Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG > registers with MSI address from advk_pcie_init_msi_irq_domain() function to > advk_pcie_setup_hw() function before enabling PCIE_CORE_CTRL2_MSI_ENABLE. > > As part of this change, also remove unused variable msi_msg, which was used > only for MSI doorbell address. MSI address can be any address which does > not conflict with PCI space. Not quite. It can be any address that cannot be used to *DMA* to. > So change it to the address of the main struct advk_pcie. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Reviewed-by: Marek Behún <kabel@kernel.org> > Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") > --- > drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------ > 1 file changed, 9 insertions(+), 12 deletions(-) > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index 5e0243b2c473..199015215779 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -195,7 +195,6 @@ struct advk_pcie { > struct msi_domain_info msi_domain_info; > DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); > struct mutex msi_used_lock; > - u16 msi_msg; > int link_gen; > struct pci_bridge_emul bridge; > struct gpio_desc *reset_gpio; > @@ -325,6 +324,7 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) > > static void advk_pcie_setup_hw(struct advk_pcie *pcie) > { > + phys_addr_t msi_addr; > u32 reg; > > /* Enable TX */ > @@ -381,6 +381,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > reg |= LANE_COUNT_1; > advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); > > + /* Set MSI address */ > + msi_addr = virt_to_phys(pcie); > + advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); > + advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); > + > /* Enable MSI */ > reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); > reg |= PCIE_CORE_CTRL2_MSI_ENABLE; > @@ -862,10 +867,10 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, > struct msi_msg *msg) > { > struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); > - phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); > + phys_addr_t msi_addr = virt_to_phys(pcie); > > - msg->address_lo = lower_32_bits(msi_msg); > - msg->address_hi = upper_32_bits(msi_msg); > + msg->address_lo = lower_32_bits(msi_addr); > + msg->address_hi = upper_32_bits(msi_addr); > msg->data = data->hwirq; > } > > @@ -960,7 +965,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) > struct device_node *node = dev->of_node; > struct irq_chip *bottom_ic, *msi_ic; > struct msi_domain_info *msi_di; > - phys_addr_t msi_msg_phys; > > mutex_init(&pcie->msi_used_lock); > > @@ -978,13 +982,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) > MSI_FLAG_MULTI_PCI_MSI; > msi_di->chip = msi_ic; > > - msi_msg_phys = virt_to_phys(&pcie->msi_msg); > - > - advk_writel(pcie, lower_32_bits(msi_msg_phys), > - PCIE_MSI_ADDR_LOW_REG); > - advk_writel(pcie, upper_32_bits(msi_msg_phys), > - PCIE_MSI_ADDR_HIGH_REG); > - > pcie->msi_inner_domain = > irq_domain_add_linear(NULL, MSI_IRQ_NUM, > &advk_msi_domain_ops, pcie); Otherwise, Acked-by: Marc Zyngier <maz@kernel.org> M. -- Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: "Pali Rohár" <pali@kernel.org> Cc: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Rob Herring" <robh@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Russell King" <rmk+kernel@armlinux.org.uk>, "Marek Behún" <kabel@kernel.org>, "Remi Pommarel" <repk@triplefau.lt>, Xogium <contact@xogium.me>, "Tomasz Maciej Nowak" <tmn505@gmail.com>, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 19/42] PCI: aardvark: Fix setting MSI address Date: Fri, 07 May 2021 11:25:30 +0100 [thread overview] Message-ID: <87a6p6q1r9.wl-maz@kernel.org> (raw) In-Reply-To: <20210506153153.30454-20-pali@kernel.org> On Thu, 06 May 2021 16:31:30 +0100, Pali Rohár <pali@kernel.org> wrote: > > MSI address for receiving MSI interrupts needs to be correctly set before > enabling processing of MSI interrupts. > > Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG > registers with MSI address from advk_pcie_init_msi_irq_domain() function to > advk_pcie_setup_hw() function before enabling PCIE_CORE_CTRL2_MSI_ENABLE. > > As part of this change, also remove unused variable msi_msg, which was used > only for MSI doorbell address. MSI address can be any address which does > not conflict with PCI space. Not quite. It can be any address that cannot be used to *DMA* to. > So change it to the address of the main struct advk_pcie. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Reviewed-by: Marek Behún <kabel@kernel.org> > Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") > --- > drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------ > 1 file changed, 9 insertions(+), 12 deletions(-) > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index 5e0243b2c473..199015215779 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -195,7 +195,6 @@ struct advk_pcie { > struct msi_domain_info msi_domain_info; > DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); > struct mutex msi_used_lock; > - u16 msi_msg; > int link_gen; > struct pci_bridge_emul bridge; > struct gpio_desc *reset_gpio; > @@ -325,6 +324,7 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) > > static void advk_pcie_setup_hw(struct advk_pcie *pcie) > { > + phys_addr_t msi_addr; > u32 reg; > > /* Enable TX */ > @@ -381,6 +381,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > reg |= LANE_COUNT_1; > advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); > > + /* Set MSI address */ > + msi_addr = virt_to_phys(pcie); > + advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); > + advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); > + > /* Enable MSI */ > reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); > reg |= PCIE_CORE_CTRL2_MSI_ENABLE; > @@ -862,10 +867,10 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, > struct msi_msg *msg) > { > struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); > - phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); > + phys_addr_t msi_addr = virt_to_phys(pcie); > > - msg->address_lo = lower_32_bits(msi_msg); > - msg->address_hi = upper_32_bits(msi_msg); > + msg->address_lo = lower_32_bits(msi_addr); > + msg->address_hi = upper_32_bits(msi_addr); > msg->data = data->hwirq; > } > > @@ -960,7 +965,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) > struct device_node *node = dev->of_node; > struct irq_chip *bottom_ic, *msi_ic; > struct msi_domain_info *msi_di; > - phys_addr_t msi_msg_phys; > > mutex_init(&pcie->msi_used_lock); > > @@ -978,13 +982,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) > MSI_FLAG_MULTI_PCI_MSI; > msi_di->chip = msi_ic; > > - msi_msg_phys = virt_to_phys(&pcie->msi_msg); > - > - advk_writel(pcie, lower_32_bits(msi_msg_phys), > - PCIE_MSI_ADDR_LOW_REG); > - advk_writel(pcie, upper_32_bits(msi_msg_phys), > - PCIE_MSI_ADDR_HIGH_REG); > - > pcie->msi_inner_domain = > irq_domain_add_linear(NULL, MSI_IRQ_NUM, > &advk_msi_domain_ops, pcie); Otherwise, Acked-by: Marc Zyngier <maz@kernel.org> M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-07 10:25 UTC|newest] Thread overview: 146+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-06 15:31 [PATCH 00/42] PCI: aardvark: Various driver fixes Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 01/42] PCI: aardvark: Fix kernel panic during PIO transfer Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-19 8:06 ` Pali Rohár 2021-05-19 8:06 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 02/42] PCI: aardvark: Fix checking for PIO Non-posted Request Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 03/42] PCI: aardvark: Fix checking for PIO status Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 04/42] PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO response Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 05/42] PCI: pci-bridge-emul: Add PCIe Root Capabilities Register Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 23:10 ` Bjorn Helgaas 2021-05-06 23:10 ` Bjorn Helgaas 2021-05-07 14:40 ` Pali Rohár 2021-05-07 14:40 ` Pali Rohár 2021-05-07 16:41 ` Bjorn Helgaas 2021-05-07 16:41 ` Bjorn Helgaas 2021-05-06 15:31 ` [PATCH 06/42] PCI: aardvark: Fix reporting CRS Software Visibility on emulated bridge Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 13:03 ` Bjorn Helgaas 2021-05-07 13:03 ` Bjorn Helgaas 2021-05-07 15:25 ` Pali Rohár 2021-05-07 15:25 ` Pali Rohár 2021-05-07 15:33 ` Pali Rohár 2021-05-07 15:33 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 07/42] PCI: aardvark: Fix link training Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 08/42] PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 09/42] PCI: aardvark: Fix PCIe Max Payload Size setting Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 10/42] PCI: aardvark: Implement workaround for the readback value of VEND_ID Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 11/42] PCI: aardvark: Do not touch status bits of masked interrupts in interrupt handler Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 12/42] PCI: aardvark: Check for virq mapping when processing INTx IRQ Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 9:15 ` Marc Zyngier 2021-05-07 9:15 ` Marc Zyngier 2021-06-04 16:24 ` Pali Rohár 2021-06-04 16:24 ` Pali Rohár 2021-06-04 16:29 ` Marc Zyngier 2021-06-04 16:29 ` Marc Zyngier 2021-05-06 15:31 ` [PATCH 13/42] PCI: aardvark: Remove irq_mask_ack callback for INTx interrupts Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 9:16 ` Marc Zyngier 2021-05-07 9:16 ` Marc Zyngier 2021-05-06 15:31 ` [PATCH 14/42] PCI: aardvark: Don't mask irq when mapping Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 9:20 ` Marc Zyngier 2021-05-07 9:20 ` Marc Zyngier 2021-05-07 9:27 ` Pali Rohár 2021-05-07 9:27 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 15/42] PCI: aardvark: Change name of INTx irq_chip to advk-INT Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 9:08 ` Marc Zyngier 2021-05-07 9:08 ` Marc Zyngier 2021-05-24 14:36 ` Marek Behún 2021-05-24 14:36 ` Marek Behún 2021-05-24 15:14 ` Marc Zyngier 2021-05-24 15:14 ` Marc Zyngier 2021-05-06 15:31 ` [PATCH 16/42] PCI: aardvark: Remove unneeded goto Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 17/42] PCI: aardvark: Fix support for MSI interrupts Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 10:16 ` Marc Zyngier 2021-05-07 10:16 ` Marc Zyngier 2021-05-07 14:44 ` Pali Rohár 2021-05-07 14:44 ` Pali Rohár 2021-05-07 16:24 ` Marc Zyngier 2021-05-07 16:24 ` Marc Zyngier 2021-06-04 16:02 ` Pali Rohár 2021-06-04 16:02 ` Pali Rohár 2021-06-04 16:22 ` Marc Zyngier 2021-06-04 16:22 ` Marc Zyngier 2021-05-06 15:31 ` [PATCH 18/42] PCI: aardvark: Correctly clear and unmask all " Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 10:19 ` Marc Zyngier 2021-05-07 10:19 ` Marc Zyngier 2021-05-07 10:21 ` Pali Rohár 2021-05-07 10:21 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 19/42] PCI: aardvark: Fix setting MSI address Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-07 10:25 ` Marc Zyngier [this message] 2021-05-07 10:25 ` Marc Zyngier 2021-05-06 15:31 ` [PATCH 20/42] PCI: aardvark: Add support for more than 32 MSI interrupts Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-07-02 21:35 ` Pali Rohár 2021-07-02 21:35 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 21/42] PCI: aardvark: Add support for masking " Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 22/42] PCI: aardvark: Enable MSI-X support Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 23/42] PCI: aardvark: Fix support for ERR interrupt on emulated bridge Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 24/42] PCI: aardvark: Fix support for PME " Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 25/42] PCI: aardvark: Fix support for PME requester " Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 26/42] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND " Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 27/42] PCI: aardvark: Disable bus mastering and mask all interrupts when unbinding driver Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 28/42] PCI: aardvark: Free config space for emulated root bridge when unbinding driver to fix memory leak Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 29/42] PCI: aardvark: Reset PCIe card and disable PHY when unbinding driver Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 30/42] PCI: aardvark: Rewrite irq code to chained irq handler Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 31/42] PCI: aardvark: Use separate INTA interrupt for emulated root bridge Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 32/42] PCI: pci-bridge-emul: Add description for class_revision field Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 33/42] PCI: pci-bridge-emul: Add definitions for missing capabilities registers Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 34/42] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 35/42] PCI: aardvark: Add support for PCI_BRIDGE_CTL_BUS_RESET " Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 36/42] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 37/42] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros by linux PCI_INTERRUPT_* values Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 38/42] PCI: aardvark: Cleanup some register macros Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 39/42] PCI: aardvark: Add comments for OB_WIN_ENABLE and ADDR_WIN_DISABLE Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 40/42] PCI: pci-bridge-emul: re-arrange register tests Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 41/42] PCI: pci-bridge-emul: add support for PCIe extended capabilities Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-05-06 15:31 ` [PATCH 42/42] PCI: aardvark: Add support for Advanced Error Reporting registers on emulated bridge Pali Rohár 2021-05-06 15:31 ` Pali Rohár 2021-06-03 15:16 ` [PATCH 00/42] PCI: aardvark: Various driver fixes Lorenzo Pieralisi 2021-06-03 15:16 ` Lorenzo Pieralisi 2021-06-03 17:02 ` Pali Rohár 2021-06-03 17:02 ` Pali Rohár 2021-06-03 18:02 ` Simon Glass 2021-06-03 18:02 ` Simon Glass 2021-06-03 18:18 ` Pali Rohár 2021-06-03 18:18 ` Pali Rohár 2021-06-04 14:05 ` Lorenzo Pieralisi 2021-06-04 14:05 ` Lorenzo Pieralisi
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