From: Valentin Schneider <valentin.schneider@arm.com> To: Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Gleixner <tglx@linutronix.de>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Vincenzo Frascino <vincenzo.frascino@arm.com> Subject: Re: [PATCH v3 05/13] genirq: Let purely flow-masked ONESHOT irqs through unmask_threaded_irq() Date: Thu, 12 Aug 2021 22:38:11 +0100 [thread overview] Message-ID: <87zgtm7398.mognet@arm.com> (raw) In-Reply-To: <87wnoq90wx.wl-maz@kernel.org> On 12/08/21 15:45, Marc Zyngier wrote: > On Thu, 12 Aug 2021 14:36:35 +0100, > Valentin Schneider <valentin.schneider@arm.com> wrote: >> >> On 12/08/21 08:26, Marc Zyngier wrote: >> > On Tue, 29 Jun 2021 13:50:02 +0100, >> > Valentin Schneider <valentin.schneider@arm.com> wrote: >> >> diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c >> >> index ef30b4762947..e6d6d32ddcbc 100644 >> >> --- a/kernel/irq/manage.c >> >> +++ b/kernel/irq/manage.c >> >> @@ -1107,7 +1107,7 @@ static void irq_finalize_oneshot(struct irq_desc *desc, >> >> desc->threads_oneshot &= ~action->thread_mask; >> >> >> >> if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && >> >> - irqd_irq_masked(&desc->irq_data)) >> >> + (irqd_irq_masked(&desc->irq_data) | irqd_irq_flow_masked(&desc->irq_data))) >> >> unmask_threaded_irq(desc); >> > >> > The bitwise OR looks pretty odd. It is probably fine given that both >> > side of the expression are bool, but still. I can fix this locally. >> > >> >> Thomas suggested that back in v1: >> >> https://lore.kernel.org/lkml/87v98v4lan.ffs@nanos.tec.linutronix.de/ >> >> I did look at the (arm64) disassembly diff back then and was convinced by >> what I saw, though I'd have to go do that again as I can't remember much >> else. > > Ah, fair enough. > Either I didn't have my glasses on or had a different output back then, but I'm not so convinced anymore... (same result on both Ubuntu GCC 9.3.0 and 10.2 GCC release from Arm): Logical OR: 8f8: b9400020 ldr w0, [x1] 8fc: 3787fea0 tbnz w0, #16, 8d0 <irq_finalize_oneshot.part.0+0x60> 900: 37880040 tbnz w0, #17, 908 <irq_finalize_oneshot.part.0+0x98> 904: 36fffe60 tbz w0, #31, 8d0 <irq_finalize_oneshot.part.0+0x60> 908: aa1303e0 mov x0, x19 90c: 94000000 bl 0 <unmask_threaded_irq> Bitwise OR (aka the patch): 8f8: b9400020 ldr w0, [x1] 8fc: 3787fea0 tbnz w0, #16, 8d0 <irq_finalize_oneshot.part.0+0x60> 900: f26f001f tst x0, #0x20000 904: 7a400801 ccmp w0, #0x0, #0x1, eq // eq = none 908: 54fffe4a b.ge 8d0 <irq_finalize_oneshot.part.0+0x60> // b.tcont 90c: aa1303e0 mov x0, x19 910: 94000000 bl 0 <unmask_threaded_irq> If I get this right... - TST sets the Z condition flag if bit 17 (masked) isn't set - CCMP sets the condition flags to - the same as SUBS(flags, 0) if bit 17 wasn't set - NZCV=0001 otherwise - B.GE branches if N==V Soooo - if we have bit 17 set, NZCV=0001, B.GE doesn't branch - if we don't have bit 17 but bit 31 (flow-masked), NZCV=1000 because this is signed 32-bit, so having bit 31 set makes the result of SUBS(flags, 0) negative, B.GE doesn't branch - if we have neither, NZCV=0XX0, B.GE branches So this does appear to do the right thing, at the cost of an extra instruction and a profound sense of dread to whoever stares at the disassembly. I guess it does save us a branch which could be mispredicted... > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Valentin Schneider <valentin.schneider@arm.com> To: Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Gleixner <tglx@linutronix.de>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Vincenzo Frascino <vincenzo.frascino@arm.com> Subject: Re: [PATCH v3 05/13] genirq: Let purely flow-masked ONESHOT irqs through unmask_threaded_irq() Date: Thu, 12 Aug 2021 22:38:11 +0100 [thread overview] Message-ID: <87zgtm7398.mognet@arm.com> (raw) In-Reply-To: <87wnoq90wx.wl-maz@kernel.org> On 12/08/21 15:45, Marc Zyngier wrote: > On Thu, 12 Aug 2021 14:36:35 +0100, > Valentin Schneider <valentin.schneider@arm.com> wrote: >> >> On 12/08/21 08:26, Marc Zyngier wrote: >> > On Tue, 29 Jun 2021 13:50:02 +0100, >> > Valentin Schneider <valentin.schneider@arm.com> wrote: >> >> diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c >> >> index ef30b4762947..e6d6d32ddcbc 100644 >> >> --- a/kernel/irq/manage.c >> >> +++ b/kernel/irq/manage.c >> >> @@ -1107,7 +1107,7 @@ static void irq_finalize_oneshot(struct irq_desc *desc, >> >> desc->threads_oneshot &= ~action->thread_mask; >> >> >> >> if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && >> >> - irqd_irq_masked(&desc->irq_data)) >> >> + (irqd_irq_masked(&desc->irq_data) | irqd_irq_flow_masked(&desc->irq_data))) >> >> unmask_threaded_irq(desc); >> > >> > The bitwise OR looks pretty odd. It is probably fine given that both >> > side of the expression are bool, but still. I can fix this locally. >> > >> >> Thomas suggested that back in v1: >> >> https://lore.kernel.org/lkml/87v98v4lan.ffs@nanos.tec.linutronix.de/ >> >> I did look at the (arm64) disassembly diff back then and was convinced by >> what I saw, though I'd have to go do that again as I can't remember much >> else. > > Ah, fair enough. > Either I didn't have my glasses on or had a different output back then, but I'm not so convinced anymore... (same result on both Ubuntu GCC 9.3.0 and 10.2 GCC release from Arm): Logical OR: 8f8: b9400020 ldr w0, [x1] 8fc: 3787fea0 tbnz w0, #16, 8d0 <irq_finalize_oneshot.part.0+0x60> 900: 37880040 tbnz w0, #17, 908 <irq_finalize_oneshot.part.0+0x98> 904: 36fffe60 tbz w0, #31, 8d0 <irq_finalize_oneshot.part.0+0x60> 908: aa1303e0 mov x0, x19 90c: 94000000 bl 0 <unmask_threaded_irq> Bitwise OR (aka the patch): 8f8: b9400020 ldr w0, [x1] 8fc: 3787fea0 tbnz w0, #16, 8d0 <irq_finalize_oneshot.part.0+0x60> 900: f26f001f tst x0, #0x20000 904: 7a400801 ccmp w0, #0x0, #0x1, eq // eq = none 908: 54fffe4a b.ge 8d0 <irq_finalize_oneshot.part.0+0x60> // b.tcont 90c: aa1303e0 mov x0, x19 910: 94000000 bl 0 <unmask_threaded_irq> If I get this right... - TST sets the Z condition flag if bit 17 (masked) isn't set - CCMP sets the condition flags to - the same as SUBS(flags, 0) if bit 17 wasn't set - NZCV=0001 otherwise - B.GE branches if N==V Soooo - if we have bit 17 set, NZCV=0001, B.GE doesn't branch - if we don't have bit 17 but bit 31 (flow-masked), NZCV=1000 because this is signed 32-bit, so having bit 31 set makes the result of SUBS(flags, 0) negative, B.GE doesn't branch - if we have neither, NZCV=0XX0, B.GE branches So this does appear to do the right thing, at the cost of an extra instruction and a profound sense of dread to whoever stares at the disassembly. I guess it does save us a branch which could be mispredicted... > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-12 21:38 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-29 12:49 [PATCH v3 00/13] irqchip/irq-gic: Optimize masking by leveraging EOImode=1 Valentin Schneider 2021-06-29 12:49 ` Valentin Schneider 2021-06-29 12:49 ` [PATCH v3 01/13] genirq: Add chip flag to denote automatic IRQ (un)masking Valentin Schneider 2021-06-29 12:49 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:49 ` [PATCH v3 02/13] genirq: Define ack_irq() and eoi_irq() helpers Valentin Schneider 2021-06-29 12:49 ` Valentin Schneider 2021-08-12 7:49 ` Marc Zyngier 2021-08-12 7:49 ` Marc Zyngier 2021-08-12 13:36 ` Valentin Schneider 2021-08-12 13:36 ` Valentin Schneider 2021-08-12 14:45 ` Marc Zyngier 2021-08-12 14:45 ` Marc Zyngier 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 03/13] genirq: Employ ack_irq() and eoi_irq() where relevant Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 04/13] genirq: Add handle_strict_flow_irq() flow handler Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 05/13] genirq: Let purely flow-masked ONESHOT irqs through unmask_threaded_irq() Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 7:26 ` Marc Zyngier 2021-08-12 7:26 ` Marc Zyngier 2021-08-12 13:36 ` Valentin Schneider 2021-08-12 13:36 ` Valentin Schneider 2021-08-12 14:45 ` Marc Zyngier 2021-08-12 14:45 ` Marc Zyngier 2021-08-12 21:38 ` Valentin Schneider [this message] 2021-08-12 21:38 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 06/13] genirq: Don't mask IRQ within flow handler if IRQ is flow-masked Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 07/13] genirq, irq-gic-v3: Make NMI flow handlers use ->irq_ack() if available Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 08/13] genirq/msi: Provide default .irq_eoi() for MSI chips Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:13 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 09/13] irqchip/gic: Rely on MSI default .irq_eoi() Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:12 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 10/13] genirq/msi: Provide default .irq_ack() for MSI chips Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:12 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 11/13] irqchip/gic: Add .irq_ack() to GIC-based irqchips Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:12 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 12/13] irqchip/gic: Convert to handle_strict_flow_irq() Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:12 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider 2021-06-29 12:50 ` [PATCH v3 13/13] irqchip/gic-v3: " Valentin Schneider 2021-06-29 12:50 ` Valentin Schneider 2021-08-12 15:12 ` [irqchip: irq/irqchip-next] " irqchip-bot for Valentin Schneider
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=87zgtm7398.mognet@arm.com \ --to=valentin.schneider@arm.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=maz@kernel.org \ --cc=tglx@linutronix.de \ --cc=vincenzo.frascino@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.