From: Chris Wilson <chris@chris-wilson.co.uk>
To: Eric Anholt <eric@anholt.net>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965
Date: Mon, 05 Jul 2010 17:39:24 +0100 [thread overview]
Message-ID: <89kc63$hc3t1l@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <87mxu5q4op.fsf@pollan.anholt.net>
On Mon, 05 Jul 2010 09:22:30 -0700, Eric Anholt <eric@anholt.net> wrote:
> On Mon, 5 Jul 2010 10:25:57 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > The original i965 requires an alignment of 128K for the display surface
> > with linear memory, so increase the requirement from 64k for these
> > chipsets. For the later chipsets in the i965 family, only a 4k alignment
> > is required. (So long as we do not start performing asynchronous flips.)
> >
> > Note the impact of this should be slight as on i965 we should be using a
> > tiled frontbuffer for anything up to a 4096x4096 display.
>
> How about G35? Does it apply to that, too?
In the section on DSP[AB]SURF it specifically lists the special case for
DevBW and DevCL. In which case, it would appear that the 128K alignment
applies for G35 as well.
* goes to tweak the patch.
-ickle
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2010-07-05 16:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-05 9:25 [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965 Chris Wilson
2010-07-05 16:22 ` Eric Anholt
2010-07-05 16:39 ` Chris Wilson [this message]
2010-07-05 17:01 ` [PATCH 1/2] drm/i915: Use 128k alignment for untiled display surface on i965 (v2) Chris Wilson
2010-07-05 17:01 ` [PATCH 2/2] drm/i915: Include any alternate names by which the device is known Chris Wilson
2010-07-05 17:08 ` Chris Wilson
2010-07-06 1:22 ` Zhenyu Wang
2010-07-08 18:28 ` Eric Anholt
2010-07-05 16:36 ` [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965 Jesse Barnes
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