From: Atish Patra <atish.patra@wdc.com> To: Christoph Hellwig <hch@infradead.org> Cc: "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "Patrick Stählin" <me@packi.ch>, "Albert Ou" <aou@eecs.berkeley.edu>, "Damien Le Moal" <Damien.LeMoal@wdc.com>, "Jason Cooper" <jason@lakedaemon.net>, "Alan Kao" <alankao@andestech.com>, "Dmitriy Cherkasov" <dmitriy@oss-tech.org>, "Anup Patel" <anup@brainfault.org>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "Zong Li" <zongbox@gmail.com>, "Palmer Dabbelt" <palmer@sifive.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Andreas Schwab" <schwab@suse.de>, "Marc Zyngier" <marc.zyngier@arm.com>, "Thomas Gleixner" <tglx@linutronix.de> Subject: Re: [v3 PATCH 8/8] RISC-V: Assign hwcap only according to boot cpu. Date: Fri, 8 Feb 2019 15:02:52 -0800 [thread overview] Message-ID: <8f5fd0c8-0320-00b1-4ddf-b1225be352c8@wdc.com> (raw) In-Reply-To: <20190208091133.GD16932@infradead.org> On 2/8/19 1:11 AM, Christoph Hellwig wrote: >> + * We don't support running Linux on hertergenous ISA systems. >> + * But first "okay" processor might not be the boot cpu. >> + * Check the ISA of boot cpu. > > Please use up your available 80 characters per line in comments. > I will fix it. >> + /* >> + * All "okay" hart should have same isa. We don't know how to >> + * handle if they don't. Throw a warning for now. >> + */ >> + if (elf_hwcap && temp_hwcap != elf_hwcap) >> + pr_warn("isa mismatch: 0x%lx != 0x%lx\n", >> + elf_hwcap, temp_hwcap); >> + >> + if (hartid == boot_cpu_hartid) >> + boot_hwcap = temp_hwcap; >> + elf_hwcap = temp_hwcap; > > So we always set elf_hwcap to the capabilities of the previous cpu. > >> + temp_hwcap = 0; > > I think tmp_hwcap should be declared and initialized inside the outer loop > instead having to manually reset it like this. > >> + } >> >> + elf_hwcap = boot_hwcap; > > And then reset it here to the boot cpu. > > Shoudn't we only report the features supported by all cores? Otherwise > we'll still have problems if the boot cpu supports a feature, but not > others. > Hmm. The other side of the argument is boot cpu does have a feature that is not supported by other hart that didn't even boot. The user space may execute something based on boot cpu capability but that won't be enabled. At least, in this way we know that we are compatible completely with boot cpu capabilities. Thoughts ? Regards, Atish > Something like: > > for () { > unsigned long this_hwcap = 0; > > for (i = 0; i < strlen(isa); i++) > this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; > > if (elf_hwcap) > elf_hwcap &= this_hwcap; > else > elf_hwcap = this_hwcap; > } > >
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atish.patra@wdc.com> To: Christoph Hellwig <hch@infradead.org> Cc: "Damien Le Moal" <Damien.LeMoal@wdc.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Jason Cooper" <jason@lakedaemon.net>, "Alan Kao" <alankao@andestech.com>, "Dmitriy Cherkasov" <dmitriy@oss-tech.org>, "Anup Patel" <anup@brainfault.org>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, "Patrick Stählin" <me@packi.ch>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "Marc Zyngier" <marc.zyngier@arm.com>, "Palmer Dabbelt" <palmer@sifive.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Andreas Schwab" <schwab@suse.de>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "Thomas Gleixner" <tglx@linutronix.de>, "Zong Li" <zongbox@gmail.com> Subject: Re: [v3 PATCH 8/8] RISC-V: Assign hwcap only according to boot cpu. Date: Fri, 8 Feb 2019 15:02:52 -0800 [thread overview] Message-ID: <8f5fd0c8-0320-00b1-4ddf-b1225be352c8@wdc.com> (raw) In-Reply-To: <20190208091133.GD16932@infradead.org> On 2/8/19 1:11 AM, Christoph Hellwig wrote: >> + * We don't support running Linux on hertergenous ISA systems. >> + * But first "okay" processor might not be the boot cpu. >> + * Check the ISA of boot cpu. > > Please use up your available 80 characters per line in comments. > I will fix it. >> + /* >> + * All "okay" hart should have same isa. We don't know how to >> + * handle if they don't. Throw a warning for now. >> + */ >> + if (elf_hwcap && temp_hwcap != elf_hwcap) >> + pr_warn("isa mismatch: 0x%lx != 0x%lx\n", >> + elf_hwcap, temp_hwcap); >> + >> + if (hartid == boot_cpu_hartid) >> + boot_hwcap = temp_hwcap; >> + elf_hwcap = temp_hwcap; > > So we always set elf_hwcap to the capabilities of the previous cpu. > >> + temp_hwcap = 0; > > I think tmp_hwcap should be declared and initialized inside the outer loop > instead having to manually reset it like this. > >> + } >> >> + elf_hwcap = boot_hwcap; > > And then reset it here to the boot cpu. > > Shoudn't we only report the features supported by all cores? Otherwise > we'll still have problems if the boot cpu supports a feature, but not > others. > Hmm. The other side of the argument is boot cpu does have a feature that is not supported by other hart that didn't even boot. The user space may execute something based on boot cpu capability but that won't be enabled. At least, in this way we know that we are compatible completely with boot cpu capabilities. Thoughts ? Regards, Atish > Something like: > > for () { > unsigned long this_hwcap = 0; > > for (i = 0; i < strlen(isa); i++) > this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; > > if (elf_hwcap) > elf_hwcap &= this_hwcap; > else > elf_hwcap = this_hwcap; > } > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-02-08 23:02 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-08 1:51 [v3 PATCH 0/8] Various SMP related fixes Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 1/8] RISC-V: Do not wait indefinitely in __cpu_up Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 9:01 ` Christoph Hellwig 2019-02-08 9:01 ` Christoph Hellwig 2019-02-08 1:51 ` [v3 PATCH 2/8] RISC-V: Move cpuid to hartid mapping to SMP Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 9:03 ` Christoph Hellwig 2019-02-08 9:03 ` Christoph Hellwig 2019-02-08 22:56 ` Atish Patra 2019-02-08 22:56 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 3/8] RISC-V: Remove NR_CPUs check during hartid search from DT Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 4/8] RISC-V: Allow hartid-to-cpuid function to fail Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 5/8] RISC-V: Compare cpuid with NR_CPUS before mapping Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 9:04 ` Christoph Hellwig 2019-02-08 9:04 ` Christoph Hellwig 2019-02-08 22:56 ` Atish Patra 2019-02-08 22:56 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 7/8] irqchip/irq-sifive-plic:: Check and continue in case of an invalid cpuid Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 1:51 ` [v3 PATCH 8/8] RISC-V: Assign hwcap only according to boot cpu Atish Patra 2019-02-08 1:51 ` Atish Patra 2019-02-08 9:11 ` Christoph Hellwig 2019-02-08 9:11 ` Christoph Hellwig 2019-02-08 23:02 ` Atish Patra [this message] 2019-02-08 23:02 ` Atish Patra 2019-02-09 4:26 ` David Abdurachmanov 2019-02-09 4:26 ` David Abdurachmanov 2019-02-09 16:11 ` Marc Zyngier 2019-02-09 16:11 ` Marc Zyngier 2019-02-11 19:02 ` Palmer Dabbelt 2019-02-11 19:02 ` Palmer Dabbelt 2019-02-11 20:03 ` Atish Patra 2019-02-11 20:03 ` Atish Patra 2019-02-11 22:13 ` Marc Zyngier 2019-02-11 22:13 ` Marc Zyngier 2019-02-11 22:23 ` Palmer Dabbelt 2019-02-11 22:23 ` Palmer Dabbelt 2019-02-11 23:25 ` Atish Patra 2019-02-11 23:25 ` Atish Patra 2019-02-11 13:23 ` Andreas Schwab 2019-02-11 13:23 ` Andreas Schwab
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