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From: Johan Jonker <jbx6244@gmail.com>
To: xxm <xxm@rock-chips.com>, Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
	devicetree@vger.kernel.org, robh+dt@kernel.org,
	Heiko Stuebner <heiko@sntech.de>
Subject: Re: [PATCH v2 1/2] dt-bindings: rockchip: Add DesignWare based PCIe controller
Date: Fri, 22 Jan 2021 15:02:38 +0100	[thread overview]
Message-ID: <9c560852-8ebf-61a6-906b-9cc8ced8bed0@gmail.com> (raw)
In-Reply-To: <31b54a67-eb1e-fa57-fff7-a0c867f27cc6@rock-chips.com>

Hi Simon,

A few comments, have a look if it is useful or that you disagree.

/////

The format of ranges in your pcie node in rk3568.dtsi and your example
is wrong!

  ranges:
    oneOf:
      - $ref: "/schemas/types.yaml#/definitions/flag"
      - minItems: 1
        maxItems: 32    # Should be enough
        items:
          minItems: 5
          maxItems: 7
          additionalItems: true
          items:
            - enum:
                - 0x01000000
                - 0x02000000
                - 0x03000000
                - 0x42000000
                - 0x43000000
                - 0x81000000
                - 0x82000000
                - 0x83000000
                - 0xc2000000
                - 0xc3000000

The array size is 3: ==> maxItems: 3
in a array a range of 5 to 7 u64 is expected.
They must start with one of the enums above!
yaml dt_check expects <> around every array member!

Old example:

ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000

0x00000800 is not in the list of above, please recheck!

          0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
          0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;

New example:
FICTION example with correct first element, but maybe NOT good for
Rockchip pcie!

ranges = <0x81000000 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>,
         <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
         <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
	
Change this also in rk3568.dtsi!

/////

rockchip_add_pcie_port()

For FTRACE filters it is needed that all functions start with the same
function prefix.

Maybe use:
rockchip_pcie_add_port()

/////

The function prefix of pcie-dw-rockchip.c is identical with functions in
pcie-rockchip-host.c
Is that OK for the maintainers?

/////

+static struct platform_driver rockchip_pcie_driver = {
+	.driver = {
+		.name	= "rk-pcie",

Maybe change to:

+		.name	= "rockchip-dw-pcie",

This name shows up in the kernel log.
Could you keep it in line with other Rockchip names, so we can filter
more easy?

dmesg | grep rockchip

rockchip-vop
rochchip-drm
etc.

+		.of_match_table = rockchip_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = rockchip_pcie_probe,
+};

/////

WARNING: multiple messages have this Message-ID (diff)
From: Johan Jonker <jbx6244@gmail.com>
To: xxm <xxm@rock-chips.com>, Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	robh+dt@kernel.org, Heiko Stuebner <heiko@sntech.de>,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2 1/2] dt-bindings: rockchip: Add DesignWare based PCIe controller
Date: Fri, 22 Jan 2021 15:02:38 +0100	[thread overview]
Message-ID: <9c560852-8ebf-61a6-906b-9cc8ced8bed0@gmail.com> (raw)
In-Reply-To: <31b54a67-eb1e-fa57-fff7-a0c867f27cc6@rock-chips.com>

Hi Simon,

A few comments, have a look if it is useful or that you disagree.

/////

The format of ranges in your pcie node in rk3568.dtsi and your example
is wrong!

  ranges:
    oneOf:
      - $ref: "/schemas/types.yaml#/definitions/flag"
      - minItems: 1
        maxItems: 32    # Should be enough
        items:
          minItems: 5
          maxItems: 7
          additionalItems: true
          items:
            - enum:
                - 0x01000000
                - 0x02000000
                - 0x03000000
                - 0x42000000
                - 0x43000000
                - 0x81000000
                - 0x82000000
                - 0x83000000
                - 0xc2000000
                - 0xc3000000

The array size is 3: ==> maxItems: 3
in a array a range of 5 to 7 u64 is expected.
They must start with one of the enums above!
yaml dt_check expects <> around every array member!

Old example:

ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000

0x00000800 is not in the list of above, please recheck!

          0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000
          0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;

New example:
FICTION example with correct first element, but maybe NOT good for
Rockchip pcie!

ranges = <0x81000000 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>,
         <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
         <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
	
Change this also in rk3568.dtsi!

/////

rockchip_add_pcie_port()

For FTRACE filters it is needed that all functions start with the same
function prefix.

Maybe use:
rockchip_pcie_add_port()

/////

The function prefix of pcie-dw-rockchip.c is identical with functions in
pcie-rockchip-host.c
Is that OK for the maintainers?

/////

+static struct platform_driver rockchip_pcie_driver = {
+	.driver = {
+		.name	= "rk-pcie",

Maybe change to:

+		.name	= "rockchip-dw-pcie",

This name shows up in the kernel log.
Could you keep it in line with other Rockchip names, so we can filter
more easy?

dmesg | grep rockchip

rockchip-vop
rochchip-drm
etc.

+		.of_match_table = rockchip_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = rockchip_pcie_probe,
+};

/////

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2021-01-22 14:04 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-20 10:15 [PATCH v2 1/2] dt-bindings: rockchip: Add DesignWare based PCIe controller Simon Xue
2021-01-20 10:15 ` Simon Xue
2021-01-20 14:07 ` Rob Herring
2021-01-20 14:07   ` Rob Herring
2021-01-20 17:07 ` Johan Jonker
2021-01-20 17:07   ` Johan Jonker
2021-01-22  2:22   ` xxm
2021-01-22  2:22     ` xxm
2021-01-22 14:02     ` Johan Jonker [this message]
2021-01-22 14:02       ` Johan Jonker
2021-01-22 15:55   ` Rob Herring
2021-01-22 15:55     ` Rob Herring
2021-01-25  1:53     ` [PATCH v2 1/2] dt-bindings: rockchip: Add DesignWare based PCIe controller【请注意,邮件由robherring2@gmail.com代发】 xxm
2021-01-25  1:53       ` xxm
2021-01-20 10:16 [PATCH v2 1/2] dt-bindings: rockchip: Add DesignWare based PCIe controller Simon Xue
2021-01-20 10:16 ` Simon Xue

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