From: "Das, Nirmoy" <nirmoy.das@linux.intel.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com>, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andi Shyti <andi.shyti@linux.intel.com>, Chris Wilson <chris.p.wilson@linux.intel.com>, Nirmoy Das <nirmoy.das@intel.com> Subject: Re: [PATCH v6 1/2] drm/i915/gt: introduce vm->scratch_range callback Date: Mon, 13 Mar 2023 13:58:27 +0100 [thread overview] Message-ID: <9c7f3d9d-5ee7-1237-8dfa-4a0699659615@linux.intel.com> (raw) In-Reply-To: <20230308-guard_error_capture-v6-1-1b5f31422563@intel.com> On 3/10/2023 10:23 AM, Andrzej Hajda wrote: > The callback will be responsible for setting scratch page PTEs for > specified range. In contrast to clear_range it cannot be optimized to nop. > It will be used by code adding guard pages. > > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 23 +++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 1 + > drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++ > 3 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index 842e69c7b21e49..38e6f0b207fe0c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -291,6 +291,27 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > ggtt->invalidate(ggtt); > } > > +static void gen8_ggtt_clear_range(struct i915_address_space *vm, > + u64 start, u64 length) > +{ > + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > + unsigned int first_entry = start / I915_GTT_PAGE_SIZE; > + unsigned int num_entries = length / I915_GTT_PAGE_SIZE; > + const gen8_pte_t scratch_pte = vm->scratch[0]->encode; > + gen8_pte_t __iomem *gtt_base = > + (gen8_pte_t __iomem *)ggtt->gsm + first_entry; > + const int max_entries = ggtt_total_entries(ggtt) - first_entry; > + int i; > + > + if (WARN(num_entries > max_entries, > + "First entry = %d; Num entries = %d (max=%d)\n", > + first_entry, num_entries, max_entries)) > + num_entries = max_entries; > + > + for (i = 0; i < num_entries; i++) > + gen8_set_pte(>t_base[i], scratch_pte); > +} > + > static void gen6_ggtt_insert_page(struct i915_address_space *vm, > dma_addr_t addr, > u64 offset, > @@ -919,6 +940,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > ggtt->vm.cleanup = gen6_gmch_remove; > ggtt->vm.insert_page = gen8_ggtt_insert_page; > ggtt->vm.clear_range = nop_clear_range; > + ggtt->vm.scratch_range = gen8_ggtt_clear_range; > > ggtt->vm.insert_entries = gen8_ggtt_insert_entries; > > @@ -1082,6 +1104,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) > ggtt->vm.clear_range = nop_clear_range; > if (!HAS_FULL_PPGTT(i915)) > ggtt->vm.clear_range = gen6_ggtt_clear_range; > + ggtt->vm.scratch_range = gen6_ggtt_clear_range; > ggtt->vm.insert_page = gen6_ggtt_insert_page; > ggtt->vm.insert_entries = gen6_ggtt_insert_entries; > ggtt->vm.cleanup = gen6_gmch_remove; > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c > index 77c793812eb46a..d6a74ae2527bd9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c > @@ -102,6 +102,7 @@ int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt) > ggtt->vm.insert_page = gmch_ggtt_insert_page; > ggtt->vm.insert_entries = gmch_ggtt_insert_entries; > ggtt->vm.clear_range = gmch_ggtt_clear_range; > + ggtt->vm.scratch_range = gmch_ggtt_clear_range; > ggtt->vm.cleanup = gmch_ggtt_remove; > > ggtt->invalidate = gmch_ggtt_invalidate; > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index 5a775310d3fcb5..69ce55f517f567 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -298,6 +298,8 @@ struct i915_address_space { > u64 start, u64 length); > void (*clear_range)(struct i915_address_space *vm, > u64 start, u64 length); > + void (*scratch_range)(struct i915_address_space *vm, > + u64 start, u64 length); > void (*insert_page)(struct i915_address_space *vm, > dma_addr_t addr, > u64 offset, >
WARNING: multiple messages have this Message-ID (diff)
From: "Das, Nirmoy" <nirmoy.das@linux.intel.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com>, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Chris Wilson <chris.p.wilson@linux.intel.com>, Nirmoy Das <nirmoy.das@intel.com> Subject: Re: [Intel-gfx] [PATCH v6 1/2] drm/i915/gt: introduce vm->scratch_range callback Date: Mon, 13 Mar 2023 13:58:27 +0100 [thread overview] Message-ID: <9c7f3d9d-5ee7-1237-8dfa-4a0699659615@linux.intel.com> (raw) In-Reply-To: <20230308-guard_error_capture-v6-1-1b5f31422563@intel.com> On 3/10/2023 10:23 AM, Andrzej Hajda wrote: > The callback will be responsible for setting scratch page PTEs for > specified range. In contrast to clear_range it cannot be optimized to nop. > It will be used by code adding guard pages. > > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 23 +++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 1 + > drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++ > 3 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index 842e69c7b21e49..38e6f0b207fe0c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -291,6 +291,27 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > ggtt->invalidate(ggtt); > } > > +static void gen8_ggtt_clear_range(struct i915_address_space *vm, > + u64 start, u64 length) > +{ > + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > + unsigned int first_entry = start / I915_GTT_PAGE_SIZE; > + unsigned int num_entries = length / I915_GTT_PAGE_SIZE; > + const gen8_pte_t scratch_pte = vm->scratch[0]->encode; > + gen8_pte_t __iomem *gtt_base = > + (gen8_pte_t __iomem *)ggtt->gsm + first_entry; > + const int max_entries = ggtt_total_entries(ggtt) - first_entry; > + int i; > + > + if (WARN(num_entries > max_entries, > + "First entry = %d; Num entries = %d (max=%d)\n", > + first_entry, num_entries, max_entries)) > + num_entries = max_entries; > + > + for (i = 0; i < num_entries; i++) > + gen8_set_pte(>t_base[i], scratch_pte); > +} > + > static void gen6_ggtt_insert_page(struct i915_address_space *vm, > dma_addr_t addr, > u64 offset, > @@ -919,6 +940,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > ggtt->vm.cleanup = gen6_gmch_remove; > ggtt->vm.insert_page = gen8_ggtt_insert_page; > ggtt->vm.clear_range = nop_clear_range; > + ggtt->vm.scratch_range = gen8_ggtt_clear_range; > > ggtt->vm.insert_entries = gen8_ggtt_insert_entries; > > @@ -1082,6 +1104,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) > ggtt->vm.clear_range = nop_clear_range; > if (!HAS_FULL_PPGTT(i915)) > ggtt->vm.clear_range = gen6_ggtt_clear_range; > + ggtt->vm.scratch_range = gen6_ggtt_clear_range; > ggtt->vm.insert_page = gen6_ggtt_insert_page; > ggtt->vm.insert_entries = gen6_ggtt_insert_entries; > ggtt->vm.cleanup = gen6_gmch_remove; > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c > index 77c793812eb46a..d6a74ae2527bd9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c > @@ -102,6 +102,7 @@ int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt) > ggtt->vm.insert_page = gmch_ggtt_insert_page; > ggtt->vm.insert_entries = gmch_ggtt_insert_entries; > ggtt->vm.clear_range = gmch_ggtt_clear_range; > + ggtt->vm.scratch_range = gmch_ggtt_clear_range; > ggtt->vm.cleanup = gmch_ggtt_remove; > > ggtt->invalidate = gmch_ggtt_invalidate; > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index 5a775310d3fcb5..69ce55f517f567 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -298,6 +298,8 @@ struct i915_address_space { > u64 start, u64 length); > void (*clear_range)(struct i915_address_space *vm, > u64 start, u64 length); > + void (*scratch_range)(struct i915_address_space *vm, > + u64 start, u64 length); > void (*insert_page)(struct i915_address_space *vm, > dma_addr_t addr, > u64 offset, >
next prev parent reply other threads:[~2023-03-13 12:59 UTC|newest] Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-10 9:23 [PATCH v6 0/2] drm/i915: add guard page to ggtt->error_capture Andrzej Hajda 2023-03-10 9:23 ` Andrzej Hajda 2023-03-10 9:23 ` [Intel-gfx] " Andrzej Hajda 2023-03-10 9:23 ` [PATCH v6 1/2] drm/i915/gt: introduce vm->scratch_range callback Andrzej Hajda 2023-03-10 9:23 ` Andrzej Hajda 2023-03-10 9:23 ` [Intel-gfx] " Andrzej Hajda 2023-03-13 12:58 ` Das, Nirmoy [this message] 2023-03-13 12:58 ` Das, Nirmoy 2023-03-14 17:14 ` Andi Shyti 2023-03-14 17:14 ` [Intel-gfx] " Andi Shyti 2023-03-14 17:14 ` Andi Shyti 2023-03-10 9:23 ` [PATCH v6 2/2] drm/i915: add guard page to ggtt->error_capture Andrzej Hajda 2023-03-10 9:23 ` Andrzej Hajda 2023-03-10 9:23 ` [Intel-gfx] " Andrzej Hajda 2023-03-13 12:58 ` Das, Nirmoy 2023-03-13 12:58 ` Das, Nirmoy 2023-03-10 11:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add guard page to ggtt->error_capture (rev8) Patchwork 2023-03-10 11:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-03-13 6:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2023-03-16 18:18 ` [Intel-gfx] [PATCH v6 0/2] drm/i915: add guard page to ggtt->error_capture Andrzej Hajda 2023-03-16 18:18 ` Andrzej Hajda
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