Re: [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support

From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: jassisinghbrar@gmail.com, robh+dt@kernel.org,
	shawnguo@kernel.org, s.hauer@pengutronix.de,
	o.rempel@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com,
	linux-imx@nxp.com, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support
Date: Wed, 26 May 2021 14:06:38 +0800	[thread overview]
Message-ID: <9d4e12dd-6462-5c9a-434a-0104bf943294@oss.nxp.com> (raw)
In-Reply-To: <20210507101926.25631-1-peng.fan@oss.nxp.com>

Hi Jassi, Shawn

On 2021/5/7 18:19, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
> It has different register layout and bit position, but the register name
> and bit definitions are almost same with previous i.MX MU.
> 
> So we extend the current imx-mailbox driver to support i.MX8ULP.

Gentle ping.. Except dt-bindings patch get A-b from Rob,no comments.
Is it ok for you to pick up this patchset?

Thanks,
Peng.

> 
> Peng Fan (4):
>    dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
>    mailbox: imx: replace the xTR/xRR array with single register
>    mailbox: imx: add xSR/xCR register array
>    mailbox: imx-mailbox: support i.MX8ULP MU
> 
>   .../devicetree/bindings/mailbox/fsl,mu.yaml   |   1 +
>   drivers/mailbox/imx-mailbox.c                 | 196 +++++++++++-------
>   2 files changed, 123 insertions(+), 74 deletions(-)
> 