RE: [RFC 0/7] cpuidle: Add poking mechanism to support non-IPI wakeup

From: Aisheng Dong <aisheng.dong@nxp.com>
To: Lucas Stach <l.stach@pengutronix.de>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Abel Vesa <abel.vesa@nxp.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Rob Herring <robh@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Fabio Estevam <fabio.estevam@nxp.com>
Cc: dl-linux-imx <linux-imx@nxp.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>
Subject: RE: [RFC 0/7] cpuidle: Add poking mechanism to support non-IPI wakeup
Date: Thu, 28 Mar 2019 11:27:53 +0000	[thread overview]
Message-ID: <AM0PR04MB4211673DC2071A6181B0948880590@AM0PR04MB4211.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1553709304.2561.44.camel@pengutronix.de>

[...]
> > > Anything that isn't visible to the GPC and requires the GIC
> > > wake_request signal to behave as specified is broken by this erratum.
> >
> > I really wonder how a timer interrupt (a PPI, hence not routed through
> > the GPC) can wake up the CPU in this case. It really feels like
> > something like "program CNTV_CVAL_EL0 to expire at some later point;
> > WFI" could result in the CPU going to a deep sleep state, and not
> > wake-up at all.
> 
> I guess it's broken in the same way. The downstream DT claims
> "local-timer-stop" for the CPU sleep state and "arm,no-tick-in-suspend"
> for the armv8-timer, which I guess is not the timer actually stopping in suspend,
> but the CPU being unable to wake up due to the timer IRQ.
> 
> > This would indicate that not only cpuidle is broken with this, but
> > absolutely every interrupt that is not routed through the GPC.
> 
> That's my understanding as well. Note that I have no NXP internal information
> and can only infer from the published reference manual, errata notice and
> downstream kernel.
> 

We will double check it.
Thanks for the information.

Regards
Dong Aisheng

> Regards,
> Lucas