All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Leo Li <leoyang.li@nxp.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller
Date: Thu, 15 Nov 2018 02:47:43 +0000	[thread overview]
Message-ID: <AM6PR04MB57813AB3D57856CDD7F5376084DC0@AM6PR04MB5781.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <AM6PR04MB5863192E246F3ED6F5812E4F8FC30@AM6PR04MB5863.eurprd04.prod.outlook.com>

Hi Leo,

> -----Original Message-----
> From: Leo Li
> Sent: 2018年11月15日 2:52
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; bhelgaas@google.com; robh+dt@kernel.org;
> mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; lorenzo.pieralisi@arm.com
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller
> 
> 
> 
> > -----Original Message-----
> > From: Z.q. Hou
> > Sent: Sunday, November 11, 2018 5:48 PM
> > To: Leo Li <leoyang.li@nxp.com>; linux-pci@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; bhelgaas@google.com; robh+dt@kernel.org;
> > mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> > shawnguo@kernel.org; lorenzo.pieralisi@arm.com
> > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > controller
> >
> > Hi Leo,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Leo Li
> > > Sent: 2018年11月9日 5:29
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > > linux-kernel@vger.kernel.org; bhelgaas@google.com;
> > > robh+dt@kernel.org; mark.rutland@arm.com;
> > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org;
> > > lorenzo.pieralisi@arm.com
> > > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > > controller
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Z.q. Hou
> > > > Sent: Tuesday, November 6, 2018 7:21 AM
> > > > To: linux-pci@vger.kernel.org;
> > > > linux-arm-kernel@lists.infradead.org;
> > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > > <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com
> > > > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q.
> > > Hou
> > > > <zhiqiang.hou@nxp.com>
> > > > Subject: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > > > controller
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > Add PCIe controller DT bindings of NXP LX series SoCs.
> > >
> > > I'm not sure if this is a good idea to name this controller LX PCIe controller.
> > > Right now, it could be true that it is only used on LX series SoCs.
> > > But I'm not sure if the LS series will not use this controller or LX
> > > series will only use this controller in the future.
> > >
> > > Since the LX series is still using the layerscape branding, so
> > > probably we should keep using the layerscape-pci.txt and define the
> > > PCIe
> > Gen4 variant?
> >
> > Yes, will add the new PCIe IP bindings to Layerscape-pci.txt.
> >
> > >
> > > Same comment for other places using the LX naming in this driver.
> >
> > Do you have any suggestion about how to name the driver and prefix of
> > structures in the driver?
> 
> Probably something like pcie-layerscape-gen4?

Thanks for your suggestion!
 
Thanks,
Zhiqiang

WARNING: multiple messages have this Message-ID (diff)
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Leo Li <leoyang.li@nxp.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>
Cc: "M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	Mingkai Hu <mingkai.hu@nxp.com>
Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller
Date: Thu, 15 Nov 2018 02:47:43 +0000	[thread overview]
Message-ID: <AM6PR04MB57813AB3D57856CDD7F5376084DC0@AM6PR04MB5781.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <AM6PR04MB5863192E246F3ED6F5812E4F8FC30@AM6PR04MB5863.eurprd04.prod.outlook.com>

Hi Leo,

> -----Original Message-----
> From: Leo Li
> Sent: 2018年11月15日 2:52
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; bhelgaas@google.com; robh+dt@kernel.org;
> mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; lorenzo.pieralisi@arm.com
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller
> 
> 
> 
> > -----Original Message-----
> > From: Z.q. Hou
> > Sent: Sunday, November 11, 2018 5:48 PM
> > To: Leo Li <leoyang.li@nxp.com>; linux-pci@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; bhelgaas@google.com; robh+dt@kernel.org;
> > mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> > shawnguo@kernel.org; lorenzo.pieralisi@arm.com
> > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > controller
> >
> > Hi Leo,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Leo Li
> > > Sent: 2018年11月9日 5:29
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > > linux-kernel@vger.kernel.org; bhelgaas@google.com;
> > > robh+dt@kernel.org; mark.rutland@arm.com;
> > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org;
> > > lorenzo.pieralisi@arm.com
> > > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > > controller
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Z.q. Hou
> > > > Sent: Tuesday, November 6, 2018 7:21 AM
> > > > To: linux-pci@vger.kernel.org;
> > > > linux-arm-kernel@lists.infradead.org;
> > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> > > > <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com
> > > > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q.
> > > Hou
> > > > <zhiqiang.hou@nxp.com>
> > > > Subject: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > > > controller
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > Add PCIe controller DT bindings of NXP LX series SoCs.
> > >
> > > I'm not sure if this is a good idea to name this controller LX PCIe controller.
> > > Right now, it could be true that it is only used on LX series SoCs.
> > > But I'm not sure if the LS series will not use this controller or LX
> > > series will only use this controller in the future.
> > >
> > > Since the LX series is still using the layerscape branding, so
> > > probably we should keep using the layerscape-pci.txt and define the
> > > PCIe
> > Gen4 variant?
> >
> > Yes, will add the new PCIe IP bindings to Layerscape-pci.txt.
> >
> > >
> > > Same comment for other places using the LX naming in this driver.
> >
> > Do you have any suggestion about how to name the driver and prefix of
> > structures in the driver?
> 
> Probably something like pcie-layerscape-gen4?

Thanks for your suggestion!
 
Thanks,
Zhiqiang
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: zhiqiang.hou@nxp.com (Z.q. Hou)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller
Date: Thu, 15 Nov 2018 02:47:43 +0000	[thread overview]
Message-ID: <AM6PR04MB57813AB3D57856CDD7F5376084DC0@AM6PR04MB5781.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <AM6PR04MB5863192E246F3ED6F5812E4F8FC30@AM6PR04MB5863.eurprd04.prod.outlook.com>

Hi Leo,

> -----Original Message-----
> From: Leo Li
> Sent: 2018?11?15? 2:52
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org;
> linux-kernel at vger.kernel.org; bhelgaas at google.com; robh+dt at kernel.org;
> mark.rutland at arm.com; l.subrahmanya at mobiveil.co.in;
> shawnguo at kernel.org; lorenzo.pieralisi at arm.com
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller
> 
> 
> 
> > -----Original Message-----
> > From: Z.q. Hou
> > Sent: Sunday, November 11, 2018 5:48 PM
> > To: Leo Li <leoyang.li@nxp.com>; linux-pci at vger.kernel.org; linux-arm-
> > kernel at lists.infradead.org; devicetree at vger.kernel.org; linux-
> > kernel at vger.kernel.org; bhelgaas at google.com; robh+dt at kernel.org;
> > mark.rutland at arm.com; l.subrahmanya at mobiveil.co.in;
> > shawnguo at kernel.org; lorenzo.pieralisi at arm.com
> > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > controller
> >
> > Hi Leo,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Leo Li
> > > Sent: 2018?11?9? 5:29
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci at vger.kernel.org;
> > > linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org;
> > > linux-kernel at vger.kernel.org; bhelgaas at google.com;
> > > robh+dt at kernel.org; mark.rutland at arm.com;
> > > l.subrahmanya at mobiveil.co.in; shawnguo at kernel.org;
> > > lorenzo.pieralisi at arm.com
> > > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: RE: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > > controller
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Z.q. Hou
> > > > Sent: Tuesday, November 6, 2018 7:21 AM
> > > > To: linux-pci at vger.kernel.org;
> > > > linux-arm-kernel at lists.infradead.org;
> > > > devicetree at vger.kernel.org; linux-kernel at vger.kernel.org;
> > > > bhelgaas at google.com; robh+dt at kernel.org; mark.rutland at arm.com;
> > > > l.subrahmanya at mobiveil.co.in; shawnguo at kernel.org; Leo Li
> > > > <leoyang.li@nxp.com>; lorenzo.pieralisi at arm.com
> > > > Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q.
> > > Hou
> > > > <zhiqiang.hou@nxp.com>
> > > > Subject: [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe
> > > > controller
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > Add PCIe controller DT bindings of NXP LX series SoCs.
> > >
> > > I'm not sure if this is a good idea to name this controller LX PCIe controller.
> > > Right now, it could be true that it is only used on LX series SoCs.
> > > But I'm not sure if the LS series will not use this controller or LX
> > > series will only use this controller in the future.
> > >
> > > Since the LX series is still using the layerscape branding, so
> > > probably we should keep using the layerscape-pci.txt and define the
> > > PCIe
> > Gen4 variant?
> >
> > Yes, will add the new PCIe IP bindings to Layerscape-pci.txt.
> >
> > >
> > > Same comment for other places using the LX naming in this driver.
> >
> > Do you have any suggestion about how to name the driver and prefix of
> > structures in the driver?
> 
> Probably something like pcie-layerscape-gen4?

Thanks for your suggestion!
 
Thanks,
Zhiqiang

  reply	other threads:[~2018-11-15  2:50 UTC|newest]

Thread overview: 103+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-06 13:19 [PATCH 00/23] PCI: refactor the Mobiveil driver and add PCIe support for NXP LX SoCs Z.q. Hou
2018-11-06 13:19 ` Z.q. Hou
2018-11-06 13:19 ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 01/23] PCI: mobiveil: uniform the register accessors Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 02/23] PCI: mobiveil: format the code without function change Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 03/23] PCI: mobiveil: correct the returned error number Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 04/23] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 05/23] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 06/23] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 07/23] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19 ` [PATCH 08/23] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:19   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 09/23] PCI: mobiveil: correct the inbound/outbound window setup routine Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 10/23] PCI: mobiveil: fix the INTx process error Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-15  2:59   ` Z.q. Hou
2018-11-15  2:59     ` Z.q. Hou
2018-11-15  2:59     ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 11/23] PCI: mobiveil: only fixup the Class Code field Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 12/23] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 13/23] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 14/23] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 15/23] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-12 18:12   ` Rob Herring
2018-11-12 18:12     ` Rob Herring
2018-11-13  6:08     ` Z.q. Hou
2018-11-13  6:08       ` Z.q. Hou
2018-11-13  6:08       ` Z.q. Hou
2018-11-14  9:33   ` Subrahmanya Lingappa
2018-11-14  9:33     ` Subrahmanya Lingappa
2018-11-15  2:27     ` Z.q. Hou
2018-11-15  2:27       ` Z.q. Hou
2018-11-15  2:27       ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 16/23] PCI: mobiveil: refactor the Mobiveil driver Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20 ` [PATCH 17/23] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:20   ` Z.q. Hou
2018-11-06 13:21 ` [PATCH 18/23] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21 ` [PATCH 19/23] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21 ` [PATCH 20/23] PCI: mobiveil: change prototype of function mobiveil_host_init Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21 ` [PATCH 21/23] dt-bindings: pci: Add NXP LX SoCs PCIe controller Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-08 21:29   ` Leo Li
2018-11-08 21:29     ` Leo Li
2018-11-08 21:29     ` Leo Li
2018-11-12  1:48     ` Z.q. Hou
2018-11-12  1:48       ` Z.q. Hou
2018-11-12  1:48       ` Z.q. Hou
2018-11-14 18:51       ` Leo Li
2018-11-14 18:51         ` Leo Li
2018-11-14 18:51         ` Leo Li
2018-11-15  2:47         ` Z.q. Hou [this message]
2018-11-15  2:47           ` Z.q. Hou
2018-11-15  2:47           ` Z.q. Hou
2018-11-06 13:21 ` [PATCH 22/23] PCI: mobiveil: add PCIe RC driver for NXP LX series SoCs Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21 ` [PATCH 23/23] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-11-06 13:21   ` Z.q. Hou
2018-12-03 11:58 ` [PATCH 00/23] PCI: refactor the Mobiveil driver and add PCIe support for NXP LX SoCs Lorenzo Pieralisi
2018-12-03 11:58   ` Lorenzo Pieralisi
2018-12-03 11:58   ` Lorenzo Pieralisi
2018-12-10 10:13   ` Subrahmanya Lingappa
2018-12-10 10:16   ` Subrahmanya Lingappa
2018-12-10 10:16     ` Subrahmanya Lingappa

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=AM6PR04MB57813AB3D57856CDD7F5376084DC0@AM6PR04MB5781.eurprd04.prod.outlook.com \
    --to=zhiqiang.hou@nxp.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=l.subrahmanya@mobiveil.co.in \
    --cc=leoyang.li@nxp.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=minghuan.lian@nxp.com \
    --cc=mingkai.hu@nxp.com \
    --cc=robh+dt@kernel.org \
    --cc=shawnguo@kernel.org \
    --cc=xiaowei.bao@nxp.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.