From: Anup Patel <anup@brainfault.org>
To: Christoph Hellwig <hch@lst.de>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode
Date: Fri, 18 Oct 2019 08:36:54 +0530 [thread overview]
Message-ID: <CAAhSdy2=WnkJV8ANW2v5s2ckDmTEZUuzegQm41-ZaEY==f1Jng@mail.gmail.com> (raw)
In-Reply-To: <20191017173743.5430-16-hch@lst.de>
On Thu, Oct 17, 2019 at 11:08 PM Christoph Hellwig <hch@lst.de> wrote:
>
> No point in bloating the kernel image with a bootloader header if
> we run bare metal.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/riscv/kernel/head.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 71efbba25ed5..dc21e409cc49 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -16,6 +16,7 @@
>
> __INIT
> ENTRY(_start)
> +#ifndef CONFIG_RISCV_M_MODE
> /*
> * Image header expected by Linux boot-loaders. The image header data
> * structure is described in asm/image.h.
> @@ -47,6 +48,7 @@ ENTRY(_start)
>
> .global _start_kernel
> _start_kernel:
> +#endif /* CONFIG_RISCV_M_MODE */
> /* Mask all interrupts */
> csrw CSR_XIE, zero
> csrw CSR_XIP, zero
> --
> 2.20.1
>
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: Christoph Hellwig <hch@lst.de>
Cc: "linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode
Date: Fri, 18 Oct 2019 08:36:54 +0530 [thread overview]
Message-ID: <CAAhSdy2=WnkJV8ANW2v5s2ckDmTEZUuzegQm41-ZaEY==f1Jng@mail.gmail.com> (raw)
In-Reply-To: <20191017173743.5430-16-hch@lst.de>
On Thu, Oct 17, 2019 at 11:08 PM Christoph Hellwig <hch@lst.de> wrote:
>
> No point in bloating the kernel image with a bootloader header if
> we run bare metal.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/riscv/kernel/head.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 71efbba25ed5..dc21e409cc49 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -16,6 +16,7 @@
>
> __INIT
> ENTRY(_start)
> +#ifndef CONFIG_RISCV_M_MODE
> /*
> * Image header expected by Linux boot-loaders. The image header data
> * structure is described in asm/image.h.
> @@ -47,6 +48,7 @@ ENTRY(_start)
>
> .global _start_kernel
> _start_kernel:
> +#endif /* CONFIG_RISCV_M_MODE */
> /* Mask all interrupts */
> csrw CSR_XIE, zero
> csrw CSR_XIP, zero
> --
> 2.20.1
>
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
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linux-riscv@lists.infradead.org
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next prev parent reply other threads:[~2019-10-18 4:54 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 17:37 RISC-V nommu support v5 Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 01/15] riscv: cleanup <asm/bug.h> Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:50 ` Anup Patel
2019-10-18 2:50 ` Anup Patel
2019-10-23 22:04 ` Paul Walmsley
2019-10-23 22:04 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 02/15] riscv: cleanup do_trap_break Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:51 ` Anup Patel
2019-10-18 2:51 ` Anup Patel
2019-10-23 22:05 ` Paul Walmsley
2019-10-23 22:05 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 03/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:51 ` Anup Patel
2019-10-18 2:51 ` Anup Patel
2019-10-18 23:55 ` Paul Walmsley
2019-10-18 23:55 ` Paul Walmsley
2019-10-28 8:12 ` Christoph Hellwig
2019-10-28 8:12 ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 04/15] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:52 ` Anup Patel
2019-10-18 2:52 ` Anup Patel
2019-10-17 17:37 ` [PATCH 05/15] riscv: poison SBI calls " Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:53 ` Anup Patel
2019-10-18 2:53 ` Anup Patel
2019-10-17 17:37 ` [PATCH 06/15] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:53 ` Anup Patel
2019-10-18 2:53 ` Anup Patel
2019-10-17 17:37 ` [PATCH 07/15] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:55 ` Anup Patel
2019-10-18 2:55 ` Anup Patel
2019-10-17 17:37 ` [PATCH 08/15] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:57 ` Anup Patel
2019-10-18 2:57 ` Anup Patel
2019-10-17 17:37 ` [PATCH 09/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:00 ` Anup Patel
2019-10-18 3:00 ` Anup Patel
2019-11-14 7:39 ` Paul Walmsley
2019-11-14 7:39 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 10/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:01 ` Anup Patel
2019-10-18 3:01 ` Anup Patel
2019-11-14 7:40 ` Paul Walmsley
2019-11-14 7:40 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 11/15] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:01 ` Anup Patel
2019-10-18 3:01 ` Anup Patel
2019-10-17 17:37 ` [PATCH 12/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:05 ` Anup Patel
2019-10-18 3:05 ` Anup Patel
2019-10-17 17:37 ` [PATCH 13/15] riscv: add nommu support Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:04 ` Anup Patel
2019-10-18 3:04 ` Anup Patel
2019-10-17 17:37 ` [PATCH 14/15] riscv: provide a flat image loader Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:06 ` Anup Patel
2019-10-18 3:06 ` Anup Patel
2019-10-17 17:37 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:06 ` Anup Patel [this message]
2019-10-18 3:06 ` Anup Patel
2019-10-18 3:08 ` RISC-V nommu support v5 Anup Patel
2019-10-18 3:08 ` Anup Patel
2019-10-18 3:29 ` Paul Walmsley
2019-10-18 3:29 ` Paul Walmsley
2019-10-18 15:25 ` Christoph Hellwig
2019-10-18 15:25 ` Christoph Hellwig
2019-10-18 23:46 ` Paul Walmsley
2019-10-18 23:46 ` Paul Walmsley
-- strict thread matches above, loose matches on Subject: below --
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-20 21:07 ` Atish Patra
2019-08-20 21:07 ` Atish Patra
2019-08-21 4:14 ` Troy Benjegerdes
2019-08-21 4:14 ` Troy Benjegerdes
2019-08-21 7:12 ` Christoph Hellwig
2019-08-21 7:12 ` Christoph Hellwig
2019-08-21 17:31 ` Atish Patra
2019-08-21 17:31 ` Atish Patra
2019-08-21 17:54 ` Troy Benjegerdes
2019-08-21 17:54 ` Troy Benjegerdes
2019-08-21 23:02 ` Anup Patel
2019-08-21 23:02 ` Anup Patel
2019-08-21 23:32 ` Troy Benjegerdes
2019-08-21 23:32 ` Troy Benjegerdes
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