From: Linus Walleij <linus.walleij@linaro.org>
To: Hyeonki Hong <hhk7734@gmail.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"open list:ARM/Amlogic Meson..."
<linux-amlogic@lists.infradead.org>
Subject: Re: [PATCH] [v2] pinctrl: meson: fix drive strength register and bit calculation
Date: Tue, 7 Jul 2020 13:15:39 +0200 [thread overview]
Message-ID: <CACRpkdZqkAXpH83H88=phtVcJRhqh-1865X8gJun_oOqBwzxrw@mail.gmail.com> (raw)
In-Reply-To: <20200618025916.GA19368@home-desktop>
On Thu, Jun 18, 2020 at 4:59 AM Hyeonki Hong <hhk7734@gmail.com> wrote:
> If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
> or more registers. However, when register and bit were calculated, the
> first register defined in the bank was used, and the bit was calculated
> based on the first pin. This causes problems in setting the driving
> strength.
>
> The following method was used to solve this problem:
> A bit is calculated first using predefined strides. Then, If the bit is
> 32 or more, the register is changed by the quotient of the bit divided
> by 32. And the bit is set to the remainder.
>
> Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
Patch applied.
Yours,
Linus Walleij
WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: Hyeonki Hong <hhk7734@gmail.com>
Cc: Kevin Hilman <khilman@baylibre.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"open list:ARM/Amlogic Meson..."
<linux-amlogic@lists.infradead.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH] [v2] pinctrl: meson: fix drive strength register and bit calculation
Date: Tue, 7 Jul 2020 13:15:39 +0200 [thread overview]
Message-ID: <CACRpkdZqkAXpH83H88=phtVcJRhqh-1865X8gJun_oOqBwzxrw@mail.gmail.com> (raw)
In-Reply-To: <20200618025916.GA19368@home-desktop>
On Thu, Jun 18, 2020 at 4:59 AM Hyeonki Hong <hhk7734@gmail.com> wrote:
> If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
> or more registers. However, when register and bit were calculated, the
> first register defined in the bank was used, and the bit was calculated
> based on the first pin. This causes problems in setting the driving
> strength.
>
> The following method was used to solve this problem:
> A bit is calculated first using predefined strides. Then, If the bit is
> 32 or more, the register is changed by the quotient of the bit divided
> by 32. And the bit is set to the remainder.
>
> Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
Patch applied.
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: Hyeonki Hong <hhk7734@gmail.com>
Cc: Kevin Hilman <khilman@baylibre.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"open list:ARM/Amlogic Meson..."
<linux-amlogic@lists.infradead.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH] [v2] pinctrl: meson: fix drive strength register and bit calculation
Date: Tue, 7 Jul 2020 13:15:39 +0200 [thread overview]
Message-ID: <CACRpkdZqkAXpH83H88=phtVcJRhqh-1865X8gJun_oOqBwzxrw@mail.gmail.com> (raw)
In-Reply-To: <20200618025916.GA19368@home-desktop>
On Thu, Jun 18, 2020 at 4:59 AM Hyeonki Hong <hhk7734@gmail.com> wrote:
> If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
> or more registers. However, when register and bit were calculated, the
> first register defined in the bank was used, and the bit was calculated
> based on the first pin. This causes problems in setting the driving
> strength.
>
> The following method was used to solve this problem:
> A bit is calculated first using predefined strides. Then, If the bit is
> 32 or more, the register is changed by the quotient of the bit divided
> by 32. And the bit is set to the remainder.
>
> Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
Patch applied.
Yours,
Linus Walleij
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2020-07-07 11:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-18 2:59 [PATCH] [v2] pinctrl: meson: fix drive strength register and bit calculation Hyeonki Hong
2020-06-18 2:59 ` Hyeonki Hong
2020-06-18 2:59 ` Hyeonki Hong
2020-07-07 11:15 ` Linus Walleij [this message]
2020-07-07 11:15 ` Linus Walleij
2020-07-07 11:15 ` Linus Walleij
2020-08-17 17:48 ` patchwork-bot+linux-amlogic
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