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From: Linus Walleij <linus.walleij@linaro.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	"open list:ARM/Amlogic Meson..."
	<linux-amlogic@lists.infradead.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Carlo Caione <carlo@caione.org>,
	Kevin Hilman <khilman@baylibre.com>
Subject: Re: [PATCH 3/3] pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals
Date: Mon, 30 Apr 2018 10:55:32 +0200	[thread overview]
Message-ID: <CACRpkdbqvq4gp58F39VeHRFdwU+O7tDUBu7L_Vg7+ZKjUy2Vtw@mail.gmail.com> (raw)
In-Reply-To: <20180422105330.4712-4-martin.blumenstingl@googlemail.com>

On Sun, Apr 22, 2018 at 12:53 PM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:

> These are only available on the Meson8m2 SoC (which uses the same
> DesignWare Ethernet MAC as Meson8b).
> The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
> PHYs or the RGMII TX clock (as far as we know the frequency is
> controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
> block).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Patch applied with Kevin's ACK.

Yours,
Linus Walleij

WARNING: multiple messages have this Message-ID (diff)
From: linus.walleij@linaro.org (Linus Walleij)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 3/3] pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals
Date: Mon, 30 Apr 2018 10:55:32 +0200	[thread overview]
Message-ID: <CACRpkdbqvq4gp58F39VeHRFdwU+O7tDUBu7L_Vg7+ZKjUy2Vtw@mail.gmail.com> (raw)
In-Reply-To: <20180422105330.4712-4-martin.blumenstingl@googlemail.com>

On Sun, Apr 22, 2018 at 12:53 PM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:

> These are only available on the Meson8m2 SoC (which uses the same
> DesignWare Ethernet MAC as Meson8b).
> The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
> PHYs or the RGMII TX clock (as far as we know the frequency is
> controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
> block).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Patch applied with Kevin's ACK.

Yours,
Linus Walleij

  reply	other threads:[~2018-04-30  8:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-22 10:53 [PATCH 0/3] pinctrl: meson: add support for the Meson8m2 SoC Martin Blumenstingl
2018-04-22 10:53 ` Martin Blumenstingl
2018-04-22 10:53 ` [PATCH 1/3] dt-bindings: " Martin Blumenstingl
2018-04-22 10:53   ` Martin Blumenstingl
2018-04-27 21:15   ` Rob Herring
2018-04-27 21:15     ` Rob Herring
2018-04-30  8:52   ` Linus Walleij
2018-04-30  8:52     ` Linus Walleij
2018-04-22 10:53 ` [PATCH 2/3] pinctrl: meson: meson8: " Martin Blumenstingl
2018-04-22 10:53   ` Martin Blumenstingl
2018-04-30  8:54   ` Linus Walleij
2018-04-30  8:54     ` Linus Walleij
2018-04-22 10:53 ` [PATCH 3/3] pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals Martin Blumenstingl
2018-04-22 10:53   ` Martin Blumenstingl
2018-04-30  8:55   ` Linus Walleij [this message]
2018-04-30  8:55     ` Linus Walleij
2018-04-27 19:11 ` [PATCH 0/3] pinctrl: meson: add support for the Meson8m2 SoC Kevin Hilman
2018-04-27 19:11   ` Kevin Hilman

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