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From: Doug Anderson <dianders@chromium.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Stephen Boyd <swboyd@chromium.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size
Date: Tue, 18 Aug 2020 07:57:38 -0700	[thread overview]
Message-ID: <CAD=FV=Vzk=qkemLRU3gaZ1K4P-9=tMqB+HUoGCQL4Zxv6q8XFQ@mail.gmail.com> (raw)
In-Reply-To: <20200818145514.16262-1-saiprakash.ranjan@codeaurora.org>

Hi,


On Tue, Aug 18, 2020 at 7:55 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
> size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
> the size and fix copy paste mistake carried over from SDM845.
>
> Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
> Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>
> Changes in v2:
>  * Edit commit msg to remove confusing references (Doug).
>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I can't validate against any datasheets, but it does what it says and
seems sane.

Reviewed-by: Douglas Anderson <dianders@chromium.org>

WARNING: multiple messages have this Message-ID (diff)
From: Doug Anderson <dianders@chromium.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Stephen Boyd <swboyd@chromium.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size
Date: Tue, 18 Aug 2020 07:57:38 -0700	[thread overview]
Message-ID: <CAD=FV=Vzk=qkemLRU3gaZ1K4P-9=tMqB+HUoGCQL4Zxv6q8XFQ@mail.gmail.com> (raw)
In-Reply-To: <20200818145514.16262-1-saiprakash.ranjan@codeaurora.org>

Hi,


On Tue, Aug 18, 2020 at 7:55 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
> size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
> the size and fix copy paste mistake carried over from SDM845.
>
> Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
> Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>
> Changes in v2:
>  * Edit commit msg to remove confusing references (Doug).
>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I can't validate against any datasheets, but it does what it says and
seems sane.

Reviewed-by: Douglas Anderson <dianders@chromium.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-08-18 14:58 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-18 14:55 [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size Sai Prakash Ranjan
2020-08-18 14:55 ` Sai Prakash Ranjan
2020-08-18 14:57 ` Doug Anderson [this message]
2020-08-18 14:57   ` Doug Anderson

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