From: Alex Deucher <alexdeucher@gmail.com>
To: amd-gfx list <amd-gfx@lists.freedesktop.org>,
Maling list - DRI developers <dri-devel@lists.freedesktop.org>,
Dave Airlie <airlied@gmail.com>,
Linux PCI <linux-pci@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: Re: [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds
Date: Wed, 4 Jul 2018 03:14:16 -0400 [thread overview]
Message-ID: <CADnq5_NQFYp6z+TaUGHSqmCh4L5LX1jiJMHM1sTux_KvM94fmA@mail.gmail.com> (raw)
In-Reply-To: <20180625210606.2736-3-alexander.deucher@amd.com>
On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Internal header used by the driver to specify pcie gen
> speeds of the asic and chipset.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anyone care to review patches 2,3,4?
> ---
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
> index 5eb895fd98bf..9cb9ceb4d74d 100644
> --- a/drivers/gpu/drm/amd/include/amd_pcie.h
> +++ b/drivers/gpu/drm/amd/include/amd_pcie.h
> @@ -27,6 +27,7 @@
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
> +#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
>
> @@ -34,6 +35,7 @@
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
> +#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
>
> --
> 2.13.6
>
WARNING: multiple messages have this Message-ID (diff)
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx list
<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
Maling list - DRI developers
<dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
Dave Airlie <airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Linux PCI <linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Cc: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds
Date: Wed, 4 Jul 2018 03:14:16 -0400 [thread overview]
Message-ID: <CADnq5_NQFYp6z+TaUGHSqmCh4L5LX1jiJMHM1sTux_KvM94fmA@mail.gmail.com> (raw)
In-Reply-To: <20180625210606.2736-3-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Internal header used by the driver to specify pcie gen
> speeds of the asic and chipset.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anyone care to review patches 2,3,4?
> ---
> drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
> index 5eb895fd98bf..9cb9ceb4d74d 100644
> --- a/drivers/gpu/drm/amd/include/amd_pcie.h
> +++ b/drivers/gpu/drm/amd/include/amd_pcie.h
> @@ -27,6 +27,7 @@
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
> +#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
> #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
>
> @@ -34,6 +35,7 @@
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
> +#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
> #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
>
> --
> 2.13.6
>
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next prev parent reply other threads:[~2018-07-04 7:14 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-25 21:06 [PATCH 0/5] drm: use core pcie functionality for pcie gen/width Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 1/5] pci: export pcie_get_speed_cap and pcie_get_width_cap Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-28 13:42 ` Bjorn Helgaas
2018-06-28 13:42 ` Bjorn Helgaas
2018-06-28 14:19 ` Alex Deucher
2018-06-28 14:19 ` Alex Deucher
2018-06-28 16:53 ` Bjorn Helgaas
2018-06-28 16:53 ` Bjorn Helgaas
2018-06-25 21:06 ` [PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-07-04 7:14 ` Alex Deucher [this message]
2018-07-04 7:14 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 3/5] drm/amdgpu: use pcie functions for link width and speed Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 4/5] drm/radeon: use pcie functions for link width Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-25 21:06 ` [PATCH 5/5] drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width Alex Deucher
2018-06-25 21:06 ` Alex Deucher
2018-06-29 19:40 ` Dave Airlie
2018-06-29 19:40 ` Dave Airlie
2018-06-29 14:59 ` [PATCH 0/5] drm: use core pcie functionality for pcie gen/width Alex Deucher
2018-06-29 14:59 ` Alex Deucher
2018-07-04 8:38 ` Christian König
2018-07-04 8:38 ` Christian König
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