From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Date: Mon, 5 Jul 2021 14:16:47 +0800 [thread overview]
Message-ID: <CAEUhbmUakAfSti1hCnLXrVBadpF-DtPkGT=LQz_f=XwmZYv2OA@mail.gmail.com> (raw)
In-Reply-To: <2675adc73be8ed35dd9d36198c519e4f46b285c2.1625202999.git.alistair.francis@wdc.com>
On Fri, Jul 2, 2021 at 1:20 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 1 +
> hw/riscv/opentitan.c | 3 +++
> 2 files changed, 4 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Date: Mon, 5 Jul 2021 14:16:47 +0800 [thread overview]
Message-ID: <CAEUhbmUakAfSti1hCnLXrVBadpF-DtPkGT=LQz_f=XwmZYv2OA@mail.gmail.com> (raw)
In-Reply-To: <2675adc73be8ed35dd9d36198c519e4f46b285c2.1625202999.git.alistair.francis@wdc.com>
On Fri, Jul 2, 2021 at 1:20 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 1 +
> hw/riscv/opentitan.c | 3 +++
> 2 files changed, 4 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-07-05 6:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 5:18 [PATCH v1 0/3] Updates to the OpenTitan machine Alistair Francis
2021-07-02 5:18 ` Alistair Francis
2021-07-02 5:19 ` [PATCH v1 1/3] char: ibex_uart: Update the register layout Alistair Francis
2021-07-02 5:19 ` Alistair Francis
2021-07-05 6:16 ` Bin Meng
2021-07-05 6:16 ` Bin Meng
2021-07-02 5:19 ` [PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-02 5:19 ` Alistair Francis
2021-07-05 6:16 ` Bin Meng [this message]
2021-07-05 6:16 ` Bin Meng
2021-07-02 5:20 ` [PATCH v1 3/3] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-02 5:20 ` Alistair Francis
2021-07-05 6:16 ` Bin Meng
2021-07-05 6:16 ` Bin Meng
2021-07-06 4:49 ` Alistair Francis
2021-07-06 4:49 ` Alistair Francis
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