From: Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
David Airlie <airlied-cv59FeDIM0c@public.gmane.org>,
Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
dri-devel
<dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
David Brown <david.brown-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
nganji-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
"Kristian H. Kristensen"
<hoegsberg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Andy Gross <andy.gross-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
dovizu-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
ryadav-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
linux-arm-msm
<linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Abhinav Kumar <abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Jordan Crouse <jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Jeykumar Sankaran
<jsanka-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
"open list:ARM/QUALCOMM SUPPORT"
<linux-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
freedreno
<freedreno-PD4FTy7X32lNgt0PjOBp9/rsn8yoX9R0@public.gmane.org>
Subject: Re: [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
Date: Mon, 9 Jul 2018 15:03:14 -0400 [thread overview]
Message-ID: <CAF6AEGtY67us7vq8_vMCfEkUDhDWFgAOZ-OAcj7JzJ=XzhpGSg@mail.gmail.com> (raw)
In-Reply-To: <20180709183515.GF20303@art_vandelay>
On Mon, Jul 9, 2018 at 2:35 PM, Sean Paul <seanpaul@chromium.org> wrote:
> On Mon, Jul 09, 2018 at 12:07:11PM -0600, Rob Herring wrote:
>> On Mon, Jul 9, 2018 at 11:40 AM Sean Paul <seanpaul@chromium.org> wrote:
>> >
>> > Signed-off-by: Sean Paul <seanpaul@chromium.org>
>> > ---
>> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++++++++++++++++++++++++++
>> > 1 file changed, 194 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > index cdaabeb3c995..339afed856de 100644
>> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > @@ -5,6 +5,8 @@
>> > * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> > */
>> >
>> > +#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
>> > +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
>> > #include <dt-bindings/interrupt-controller/arm-gic.h>
>> >
>> > / {
>> > @@ -221,6 +223,198 @@
>> > #interrupt-cells = <2>;
>> > };
>> >
>> > + mdss: mdss@ae00000 {
>> > + compatible = "qcom,dpu-mdss";
>> > + reg = <0xae00000 0x1000>;
>> > + reg-names = "mdss_phys";
>> > +
>> > + power-domains = <&dispcc 0>;
>> > +
>> > + clocks = <&gcc GCC_DISP_AHB_CLK>,
>> > + <&gcc GCC_DISP_AXI_CLK>,
>> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> > + clock-names = "iface", "bus", "core";
>> > + clock-frequency = <0 0 300000000>;
>> > +
>> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> > + interrupt-controller;
>> > + #interrupt-cells = <1>;
>> > +
>> > + /* iommus = <&apps_iommu 0>; */
>> > +
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > + ranges;
>> > +
>> > + mdss_mdp: mdp@ae01000 {
>> > + compatible = "qcom,dpu";
>>
>
> Hi Rob,
> Thanks for the quick turnaround! In addition to below, I'll also beef up the
> commit message, since I forgot to add any description of the change.
>
>
>> Needs an SoC specific compatible. Did this binding get reviewed?
>>
>
> No, it's part of this set ([PATCH 19/21] dt-bindings: msm/disp: Add bindings for
> Snapdragon 845 DPU).
note that for display controller and DSI we've been able to reliably
read the version of the block from hardware.
BR,
-R
>
>> > + reg = <0x0ae01000 0x8f000>,
>> > + <0x0aeb0000 0x2008>;
>> > + reg-names = "mdp_phys", "vbif_phys";
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AXI_CLK>,
>> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> > + clock-names = "iface", "bus", "core", "vsync";
>> > + clock-frequency = <0 0 300000000 19200000>;
>>
>> That's abusing clock-frequency which is generally 1 value. Use
>> assigned-clock-rates instead.
>>
>
> Thanks, will change.
>
>> > +
>> > + interrupt-parent = <&mdss>;
>> > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + port@0 {
>> > + reg = <0>;
>> > + dpu_intf1_out: endpoint {
>> > + remote-endpoint = <&dsi0_in>;
>> > + };
>> > + };
>> > +
>> > + port@1 {
>> > + reg = <1>;
>> > + dpu_intf2_out: endpoint {
>> > + remote-endpoint = <&dsi1_in>;
>> > + };
>> > + };
>> > + };
>> > + };
>> > +
>> > + dsi0: dsi@ae94000 {
>> > + compatible = "qcom,mdss-dsi-ctrl";
>>
>> Needs an SoC specific compatible.
>>
>
> Ok, will add.
>
>> > + reg = <0xae94000 0x400>;
>> > + reg-names = "dsi_ctrl";
>> > +
>> > + interrupt-parent = <&mdss>;
>> > + interrupts = <4 0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AXI_CLK>;
>> > + clock-names = "byte_clk",
>> > + "byte_intf_clk",
>> > + "pixel_clk",
>> > + "core_clk",
>> > + "iface_clk",
>> > + "bus_clk";
>>
>> Should have found this in binding review, but the "_clk" part is redundant.
>>
>
> This binding is already in mainline (Documentation/devicetree/bindings/display/msm/dsi.txt),
> which is why _clk is here, but not above.
>
> Sean
>> > +
>> > + phys = <&dsi0_phy>;
>> > + phy-names = "dsi-phy";
>> > +
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + port@0 {
>> > + reg = <0>;
>> > + dsi0_in: endpoint {
>> > + remote-endpoint = <&dpu_intf1_out>;
>> > + };
>> > + };
>> > +
>> > + port@1 {
>> > + reg = <1>;
>> > + dsi0_out: endpoint {
>> > + };
>> > + };
>> > + };
>> > + };
>> > +
>> > + dsi0_phy: dsi-phy@ae94400 {
>> > + compatible = "qcom,dsi-phy-10nm";
>> > + reg = <0xae94400 0x200>,
>> > + <0xae94a00 0x1e0>,
>> > + <0xae94600 0x280>;
>> > + reg-names = "dsi_phy",
>> > + "dsi_pll",
>> > + "dsi_phy_lane";
>> > +
>> > + #clock-cells = <1>;
>> > + #phy-cells = <0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
>> > + clock-names = "iface_clk";
>> > + };
>> > +
>> > + dsi1: dsi@ae96000 {
>> > + compatible = "qcom,mdss-dsi-ctrl";
>> > + reg = <0xae96000 0x400>;
>> > + reg-names = "dsi_ctrl";
>> > +
>> > + interrupt-parent = <&mdss>;
>> > + interrupts = <5 0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
>> > + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
>> > + <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
>> > + <&dispcc DISP_CC_MDSS_ESC1_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AXI_CLK>;
>> > + clock-names = "byte_clk",
>> > + "byte_intf_clk",
>> > + "pixel_clk",
>> > + "core_clk",
>> > + "iface_clk",
>> > + "bus_clk";
>> > +
>> > + phys = <&dsi1_phy>;
>> > + phy-names = "dsi-phy";
>> > +
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + port@0 {
>> > + reg = <0>;
>> > + dsi1_in: endpoint {
>> > + remote-endpoint = <&dpu_intf2_out>;
>> > + };
>> > + };
>> > +
>> > + port@1 {
>> > + reg = <1>;
>> > + dsi1_out: endpoint {
>> > + };
>> > + };
>> > + };
>> > + };
>> > +
>> > + dsi1_phy: dsi-phy@ae96400 {
>> > + compatible = "qcom,dsi-phy-10nm";
>> > + reg = <0xae96400 0x200>,
>> > + <0xae96a00 0x10e>,
>> > + <0xae96600 0x280>;
>> > + reg-names = "dsi_phy",
>> > + "dsi_pll",
>> > + "dsi_phy_lane";
>> > +
>> > + #clock-cells = <1>;
>> > + #phy-cells = <0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
>> > + clock-names = "iface_clk";
>> > + };
>> > + };
>> > +
>> > + dispcc: qcom,dispcc@af00000 {
>> > + compatible = "qcom,sdm845-dispcc";
>> > + reg = <0xaf00000 0x10000>;
>> > + #clock-cells = <1>;
>> > + #reset-cells = <1>;
>> > + #power-domain-cells = <1>;
>> > + };
>> > +
>> > spmi_bus: spmi@c440000 {
>> > compatible = "qcom,spmi-pmic-arb";
>> > reg = <0xc440000 0x1100>,
>> > --
>> > Sean Paul, Software Engineer, Google / Chromium OS
>> >
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
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WARNING: multiple messages have this Message-ID (diff)
From: robdclark@gmail.com (Rob Clark)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
Date: Mon, 9 Jul 2018 15:03:14 -0400 [thread overview]
Message-ID: <CAF6AEGtY67us7vq8_vMCfEkUDhDWFgAOZ-OAcj7JzJ=XzhpGSg@mail.gmail.com> (raw)
In-Reply-To: <20180709183515.GF20303@art_vandelay>
On Mon, Jul 9, 2018 at 2:35 PM, Sean Paul <seanpaul@chromium.org> wrote:
> On Mon, Jul 09, 2018 at 12:07:11PM -0600, Rob Herring wrote:
>> On Mon, Jul 9, 2018 at 11:40 AM Sean Paul <seanpaul@chromium.org> wrote:
>> >
>> > Signed-off-by: Sean Paul <seanpaul@chromium.org>
>> > ---
>> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++++++++++++++++++++++++++
>> > 1 file changed, 194 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > index cdaabeb3c995..339afed856de 100644
>> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> > @@ -5,6 +5,8 @@
>> > * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> > */
>> >
>> > +#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
>> > +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
>> > #include <dt-bindings/interrupt-controller/arm-gic.h>
>> >
>> > / {
>> > @@ -221,6 +223,198 @@
>> > #interrupt-cells = <2>;
>> > };
>> >
>> > + mdss: mdss at ae00000 {
>> > + compatible = "qcom,dpu-mdss";
>> > + reg = <0xae00000 0x1000>;
>> > + reg-names = "mdss_phys";
>> > +
>> > + power-domains = <&dispcc 0>;
>> > +
>> > + clocks = <&gcc GCC_DISP_AHB_CLK>,
>> > + <&gcc GCC_DISP_AXI_CLK>,
>> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> > + clock-names = "iface", "bus", "core";
>> > + clock-frequency = <0 0 300000000>;
>> > +
>> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> > + interrupt-controller;
>> > + #interrupt-cells = <1>;
>> > +
>> > + /* iommus = <&apps_iommu 0>; */
>> > +
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > + ranges;
>> > +
>> > + mdss_mdp: mdp at ae01000 {
>> > + compatible = "qcom,dpu";
>>
>
> Hi Rob,
> Thanks for the quick turnaround! In addition to below, I'll also beef up the
> commit message, since I forgot to add any description of the change.
>
>
>> Needs an SoC specific compatible. Did this binding get reviewed?
>>
>
> No, it's part of this set ([PATCH 19/21] dt-bindings: msm/disp: Add bindings for
> Snapdragon 845 DPU).
note that for display controller and DSI we've been able to reliably
read the version of the block from hardware.
BR,
-R
>
>> > + reg = <0x0ae01000 0x8f000>,
>> > + <0x0aeb0000 0x2008>;
>> > + reg-names = "mdp_phys", "vbif_phys";
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AXI_CLK>,
>> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> > + clock-names = "iface", "bus", "core", "vsync";
>> > + clock-frequency = <0 0 300000000 19200000>;
>>
>> That's abusing clock-frequency which is generally 1 value. Use
>> assigned-clock-rates instead.
>>
>
> Thanks, will change.
>
>> > +
>> > + interrupt-parent = <&mdss>;
>> > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + port at 0 {
>> > + reg = <0>;
>> > + dpu_intf1_out: endpoint {
>> > + remote-endpoint = <&dsi0_in>;
>> > + };
>> > + };
>> > +
>> > + port at 1 {
>> > + reg = <1>;
>> > + dpu_intf2_out: endpoint {
>> > + remote-endpoint = <&dsi1_in>;
>> > + };
>> > + };
>> > + };
>> > + };
>> > +
>> > + dsi0: dsi at ae94000 {
>> > + compatible = "qcom,mdss-dsi-ctrl";
>>
>> Needs an SoC specific compatible.
>>
>
> Ok, will add.
>
>> > + reg = <0xae94000 0x400>;
>> > + reg-names = "dsi_ctrl";
>> > +
>> > + interrupt-parent = <&mdss>;
>> > + interrupts = <4 0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AXI_CLK>;
>> > + clock-names = "byte_clk",
>> > + "byte_intf_clk",
>> > + "pixel_clk",
>> > + "core_clk",
>> > + "iface_clk",
>> > + "bus_clk";
>>
>> Should have found this in binding review, but the "_clk" part is redundant.
>>
>
> This binding is already in mainline (Documentation/devicetree/bindings/display/msm/dsi.txt),
> which is why _clk is here, but not above.
>
> Sean
>> > +
>> > + phys = <&dsi0_phy>;
>> > + phy-names = "dsi-phy";
>> > +
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + port at 0 {
>> > + reg = <0>;
>> > + dsi0_in: endpoint {
>> > + remote-endpoint = <&dpu_intf1_out>;
>> > + };
>> > + };
>> > +
>> > + port at 1 {
>> > + reg = <1>;
>> > + dsi0_out: endpoint {
>> > + };
>> > + };
>> > + };
>> > + };
>> > +
>> > + dsi0_phy: dsi-phy at ae94400 {
>> > + compatible = "qcom,dsi-phy-10nm";
>> > + reg = <0xae94400 0x200>,
>> > + <0xae94a00 0x1e0>,
>> > + <0xae94600 0x280>;
>> > + reg-names = "dsi_phy",
>> > + "dsi_pll",
>> > + "dsi_phy_lane";
>> > +
>> > + #clock-cells = <1>;
>> > + #phy-cells = <0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
>> > + clock-names = "iface_clk";
>> > + };
>> > +
>> > + dsi1: dsi at ae96000 {
>> > + compatible = "qcom,mdss-dsi-ctrl";
>> > + reg = <0xae96000 0x400>;
>> > + reg-names = "dsi_ctrl";
>> > +
>> > + interrupt-parent = <&mdss>;
>> > + interrupts = <5 0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
>> > + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
>> > + <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
>> > + <&dispcc DISP_CC_MDSS_ESC1_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> > + <&dispcc DISP_CC_MDSS_AXI_CLK>;
>> > + clock-names = "byte_clk",
>> > + "byte_intf_clk",
>> > + "pixel_clk",
>> > + "core_clk",
>> > + "iface_clk",
>> > + "bus_clk";
>> > +
>> > + phys = <&dsi1_phy>;
>> > + phy-names = "dsi-phy";
>> > +
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + port at 0 {
>> > + reg = <0>;
>> > + dsi1_in: endpoint {
>> > + remote-endpoint = <&dpu_intf2_out>;
>> > + };
>> > + };
>> > +
>> > + port at 1 {
>> > + reg = <1>;
>> > + dsi1_out: endpoint {
>> > + };
>> > + };
>> > + };
>> > + };
>> > +
>> > + dsi1_phy: dsi-phy at ae96400 {
>> > + compatible = "qcom,dsi-phy-10nm";
>> > + reg = <0xae96400 0x200>,
>> > + <0xae96a00 0x10e>,
>> > + <0xae96600 0x280>;
>> > + reg-names = "dsi_phy",
>> > + "dsi_pll",
>> > + "dsi_phy_lane";
>> > +
>> > + #clock-cells = <1>;
>> > + #phy-cells = <0>;
>> > +
>> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
>> > + clock-names = "iface_clk";
>> > + };
>> > + };
>> > +
>> > + dispcc: qcom,dispcc at af00000 {
>> > + compatible = "qcom,sdm845-dispcc";
>> > + reg = <0xaf00000 0x10000>;
>> > + #clock-cells = <1>;
>> > + #reset-cells = <1>;
>> > + #power-domain-cells = <1>;
>> > + };
>> > +
>> > spmi_bus: spmi at c440000 {
>> > compatible = "qcom,spmi-pmic-arb";
>> > reg = <0xc440000 0x1100>,
>> > --
>> > Sean Paul, Software Engineer, Google / Chromium OS
>> >
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
next prev parent reply other threads:[~2018-07-09 19:03 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-09 17:31 [PATCH 00/21] drm/msm: Add support for SDM845 Display Processing Unit (DPU) Sean Paul
2018-07-09 17:31 ` [PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding Sean Paul
[not found] ` <20180709173200.238457-2-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-20 14:13 ` Rob Herring
2018-07-09 17:31 ` [PATCH 05/21] drm/msm/dsi: adjust dsi timing for dual dsi mode Sean Paul
[not found] ` <20180709173200.238457-6-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 14:17 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 06/21] drm/msm/dsi: Use one connector for dual DSI mode Sean Paul
2018-07-09 17:31 ` [PATCH 17/21] drm/msm: Add preclose kms hook Sean Paul
2018-07-09 17:31 ` [PATCH 19/21] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
[not found] ` <20180709173200.238457-20-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-12 21:08 ` [PATCH v2 " Sean Paul
[not found] ` <20180712210849.146638-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 16:21 ` Rob Herring
[not found] ` <20180709173200.238457-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-09 17:31 ` [PATCH 02/21] dt-bindings: clock: Introduce QCOM Display clock bindings Sean Paul
2018-07-09 17:31 ` Sean Paul
2018-07-09 17:31 ` [PATCH 03/21] drm: Add support for pps and compression mode command packet Sean Paul
2018-07-09 17:31 ` Sean Paul
2018-07-09 17:31 ` Sean Paul
2018-07-09 17:31 ` [PATCH 04/21] drm: add msm compressed format modifiers Sean Paul
[not found] ` <20180709173200.238457-5-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 12:28 ` Rob Clark
2018-07-09 17:31 ` [PATCH 07/21] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll Sean Paul
[not found] ` <20180709173200.238457-8-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 14:28 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 08/21] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks Sean Paul
2018-07-09 17:31 ` [PATCH 09/21] drm/msm/mdp5: subclass msm_mdss for mdp5 Sean Paul
[not found] ` <20180709173200.238457-10-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 14:40 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 10/21] drm/msm: enable zpos normalization Sean Paul
2018-07-09 17:31 ` [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Sean Paul
2018-07-16 14:46 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 12/21] drm/msm: Clean up dangling atomic_wq Sean Paul
2018-07-09 17:31 ` [PATCH 13/21] drm/msm: #define MDP version numbers Sean Paul
2018-07-09 17:31 ` [PATCH 14/21] drm/msm: Use labels for unwinding in the error path Sean Paul
2018-07-09 17:31 ` [PATCH 15/21] drm/msm: #define MAX_<OBJECT> in msm_drv.h Sean Paul
2018-07-09 17:31 ` [PATCH 16/21] drm/msm: Add .commit() callback to msm_kms functions Sean Paul
2018-07-09 17:31 ` [PATCH 18/21] drm/msm: Add pm_suspend/resume callbacks to msm_kms Sean Paul
2018-07-09 17:31 ` [PATCH 20/21] drm/msm: Add SDM845 DPU support Sean Paul
2018-07-09 17:31 ` [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file Sean Paul
2018-07-09 17:31 ` Sean Paul
2018-07-09 18:07 ` Rob Herring
2018-07-09 18:07 ` Rob Herring
2018-07-09 18:35 ` Sean Paul
2018-07-09 18:35 ` Sean Paul
2018-07-09 19:03 ` Rob Clark [this message]
2018-07-09 19:03 ` Rob Clark
2018-07-12 21:13 ` [PATCH v2 " Sean Paul
2018-07-12 21:13 ` Sean Paul
2018-07-10 15:45 ` [PATCH 20/21] drm/msm: Add SDM845 DPU support Sean Paul
2018-07-16 14:03 ` Rob Clark
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