Re: [Intel-gfx] [PATCH 00/11] drm/msm: A5XX preemption

From: Rob Clark <robdclark@gmail.com>
To: Daniel Stone <daniel@fooishbar.org>
Cc: Daniel Vetter <daniel@ffwll.ch>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	freedreno@lists.freedesktop.org,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH 00/11] drm/msm: A5XX preemption
Date: Mon, 6 Feb 2017 13:29:06 -0500	[thread overview]
Message-ID: <CAF6AEGvVqcfvr5vdsPt3cJWOyrgd5s5=67HZSkUKjEm=J94J-w@mail.gmail.com> (raw)
In-Reply-To: <CAPj87rP=UOhfVDSGh=eDrsYENumeUBYhkEEew9At2w3Q9mbs3Q@mail.gmail.com>

On Mon, Feb 6, 2017 at 1:23 PM, Daniel Stone <daniel@fooishbar.org> wrote:
> Hi,
>
> On 6 February 2017 at 17:59, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote:
>>> This initial series implements 4 ringbuffers to give sufficient coverage for the
>>> range of priority levels requested by the GLES and compute extensions. The
>>> targeted ringbuffer is specified in the command submission flags. The default
>>> ring is 0 (lowest priority).
>>
>> Link to userspace part that implements these extensions? Also which
>> gles/compute extensions are you talking about? Asking not just because of
>> the open source userspace requirement, but also because we want to
>> upstream a scheduler on the i915 side. Getting alignment on that across
>> drm drivers would be sweet.
>
> Assuming he meant EGL rather than GLES, this is the usual one:
> https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt
>

There was an RFC for this from Chris.. not sure if it landed yet, but
that is what I was planning to use from the userspace side.

Probably first step would be to enable this without preemption points.
Although I think I have a reasonable idea how the preemption points
work..

BR,
-R