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From: Peter Maydell <peter.maydell@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Bin Meng" <bin.meng@windriver.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-arm <qemu-arm@nongnu.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>
Subject: Re: [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model
Date: Thu, 28 Jan 2021 13:51:38 +0000	[thread overview]
Message-ID: <CAFEAcA-yMfP27RKyDyUqNcnwArxnPcSV6z2U3AC-FCM4WisbpA@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmWutywRhPNRQJccfo+ojUFL=P4K334zG7L=ZtdjwM_tTA@mail.gmail.com>

On Thu, 28 Jan 2021 at 07:15, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Jan 22, 2021 at 9:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Jan 19, 2021 at 9:40 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > From: Bin Meng <bin.meng@windriver.com>
> > >
> > > This v8 series is based on the following 2 versions:
> > >
> > > - v5 series sent from Bin
> > >   http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919
> > > - v7 series sent from Philippe
> > >   http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612
> > >
> > > This series fixes a bunch of bugs in current implementation of the imx
> > > spi controller, including the following issues:
> > >
> > > - remove imx_spi_update_irq() in imx_spi_reset()
> > > - chip select signal was not lower down when spi controller is disabled
> > > - round up the tx burst length to be multiple of 8
> > > - transfer incorrect data when the burst length is larger than 32 bit
> > > - spi controller tx and rx fifo endianness is incorrect
> > > - remove pointless variable (s->burst_length) initialization (Philippe)
> > > - rework imx_spi_reset() to keep CONREG register value (Philippe)
> > > - rework imx_spi_read() to handle block disabled (Philippe)
> > > - rework imx_spi_write() to handle block disabled (Philippe)
> > >
> > > Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7
> > > (interrupt mode).
> > >
> > > Changes in v8:
> > > - keep the controller disable logic in the ECSPI_CONREG case
> > >   in imx_spi_write()
> >
> > Ping?
>
> Could we get this applied soon if no more comments?

Sorry, I think I missed this re-send. I've reviewed or left
comments on the patches that were still unreviewed.

thanks
-- PMM


      reply	other threads:[~2021-01-28 13:54 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-19 13:38 [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-19 13:38 ` [PATCH v8 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Bin Meng
2021-01-19 13:38 ` [PATCH v8 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Bin Meng
2021-01-28 13:34   ` Peter Maydell
2021-01-19 13:38 ` [PATCH v8 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Bin Meng
2021-01-19 13:39 ` [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Bin Meng
2021-01-28 13:43   ` Peter Maydell
2021-01-28 13:46     ` Bin Meng
2021-01-28 13:54       ` Peter Maydell
2021-01-28 14:15         ` Bin Meng
2021-01-28 14:17         ` Philippe Mathieu-Daudé
2021-01-28 14:22           ` Peter Maydell
2021-01-28 14:32             ` Philippe Mathieu-Daudé
2021-01-28 14:41               ` Peter Maydell
2021-01-28 14:49                 ` Philippe Mathieu-Daudé
2021-01-28 15:00                   ` Bin Meng
2021-01-19 13:39 ` [PATCH v8 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Bin Meng
2021-01-19 13:39 ` [PATCH v8 06/10] hw/ssi: imx_spi: Rework imx_spi_write() " Bin Meng
2021-01-28 13:34   ` Peter Maydell
2021-01-19 13:39 ` [PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Bin Meng
2021-01-19 13:39 ` [PATCH v8 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Bin Meng
2021-01-28 13:50   ` Peter Maydell
2021-01-19 13:39 ` [PATCH v8 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-19 13:39 ` [PATCH v8 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng
2021-01-28 13:32   ` Peter Maydell
2021-01-22 13:36 ` [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-28  7:15   ` Bin Meng
2021-01-28 13:51     ` Peter Maydell [this message]

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